From 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 17:08:55 -0700
Subject: More literal/width rangling.

---
 src/test/scala/chiselTests/Stack.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/Stack.scala')

diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 440228c9..0c84e62a 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -16,7 +16,7 @@ class ChiselStack(val depth: Int) extends Module {
     val dataOut = Output(UInt.width(32))
   })
 
-  val stack_mem = Mem(depth, UInt(width = 32))
+  val stack_mem = Mem(depth, UInt.width(32))
   val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
   val out       = Reg(init = UInt(0, width = 32))
 
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