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authorJim Lawson2016-06-21 10:13:51 -0700
committerJim Lawson2016-06-21 10:13:51 -0700
commit083610b2faa456dfccc4365dd115565d36e522fa (patch)
tree40df9237ddc8789f24d924c0cfa63a066fcc1f1c /src/test/scala/chiselTests/Stack.scala
parentd675043717593fb7e96fb0f1952debbeb7f20a57 (diff)
Most of the remaining tests with Module, IO wrapping.
Diffstat (limited to 'src/test/scala/chiselTests/Stack.scala')
-rw-r--r--src/test/scala/chiselTests/Stack.scala14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index ac799c8a..46e5dc23 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -5,13 +5,13 @@ import scala.collection.mutable.Stack
import Chisel._
class ChiselStack(val depth: Int) extends Module {
- val io = new Bundle {
- val push = Bool(INPUT)
- val pop = Bool(INPUT)
- val en = Bool(INPUT)
- val dataIn = UInt(INPUT, 32)
- val dataOut = UInt(OUTPUT, 32)
- }
+ val io = IO(new Bundle {
+ val push = Input(Bool())
+ val pop = Input(Bool())
+ val en = Input(Bool())
+ val dataIn = Input(UInt(32))
+ val dataOut = Output(UInt(32))
+ })
val stack_mem = Mem(depth, UInt(width = 32))
val sp = Reg(init = UInt(0, width = log2Up(depth + 1)))