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-rw-r--r--chiselFrontend/src/main/scala/Chisel/Printf.scala4
-rw-r--r--src/main/scala/Chisel/util/Arbiter.scala14
-rw-r--r--src/test/scala/chiselTests/BlackBox.scala32
-rw-r--r--src/test/scala/chiselTests/ComplexAssign.scala10
-rw-r--r--src/test/scala/chiselTests/Direction.scala8
-rw-r--r--src/test/scala/chiselTests/GCD.scala14
-rw-r--r--src/test/scala/chiselTests/MemorySearch.scala12
-rw-r--r--src/test/scala/chiselTests/MulLookup.scala10
-rw-r--r--src/test/scala/chiselTests/Padding.scala10
-rw-r--r--src/test/scala/chiselTests/Stack.scala14
-rw-r--r--src/test/scala/chiselTests/UIntOps.scala50
-rw-r--r--src/test/scala/chiselTests/VectorPacketIO.scala9
12 files changed, 94 insertions, 93 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/Printf.scala b/chiselFrontend/src/main/scala/Chisel/Printf.scala
index f068f637..cc121eac 100644
--- a/chiselFrontend/src/main/scala/Chisel/Printf.scala
+++ b/chiselFrontend/src/main/scala/Chisel/Printf.scala
@@ -24,13 +24,13 @@ object printf { // scalastyle:ignore object.name
* @param data format string varargs containing data to print
*/
def apply(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
- when (!(Builder.dynamicContext.currentModule.get.reset)) {
+ when (!Builder.forcedModule.reset) {
printfWithoutReset(fmt, data:_*)
}
}
private[Chisel] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
- val clock = Builder.dynamicContext.currentModule.get.clock
+ val clock = Builder.forcedModule.clock
pushCommand(Printf(sourceInfo, Node(clock), fmt, data.map((d: Bits) => d.ref)))
}
}
diff --git a/src/main/scala/Chisel/util/Arbiter.scala b/src/main/scala/Chisel/util/Arbiter.scala
index 16ae9be5..5cef4b24 100644
--- a/src/main/scala/Chisel/util/Arbiter.scala
+++ b/src/main/scala/Chisel/util/Arbiter.scala
@@ -7,9 +7,9 @@ package Chisel
/** An I/O bundle for the Arbiter */
class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
- val in = Vec(n, Decoupled(gen)).flip
- val out = Decoupled(gen)
- val chosen = UInt(OUTPUT, log2Up(n))
+ val in = Flipped(Vec(n, DecoupledIO(gen)))
+ val out = DecoupledIO(gen)
+ val chosen = Output(UInt(log2Up(n)))
}
/** Arbiter Control determining which producer has access */
@@ -25,7 +25,7 @@ private object ArbiterCtrl
abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module {
def grant: Seq[Bool]
def choice: UInt
- val io = new ArbiterIO(gen, n)
+ val io = IO(new ArbiterIO(gen, n))
io.chosen := choice
io.out.valid := io.in(io.chosen).valid
@@ -37,7 +37,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
val locked = lockCount.value =/= UInt(0)
val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
- when (io.out.fire() && wantsLock) {
+ when (io.out.firing && wantsLock) {
lockIdx := io.chosen
lockCount.inc()
}
@@ -53,7 +53,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
extends LockingArbiterLike[T](gen, n, count, needsLock) {
- lazy val lastGrant = RegEnable(io.chosen, io.out.fire())
+ lazy val lastGrant = RegEnable(io.chosen, io.out.firing)
lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
@@ -99,7 +99,7 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
consumer.io.in <> arb.io.out
*/
class Arbiter[T <: Data](gen: T, n: Int) extends Module {
- val io = new ArbiterIO(gen, n)
+ val io = IO(new ArbiterIO(gen, n))
io.chosen := UInt(n-1)
io.out.bits := io.in(n-1).bits
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index ca94087c..5877149f 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -8,25 +8,25 @@ import Chisel._
import Chisel.testers.BasicTester
class BlackBoxInverter extends BlackBox {
- val io = new Bundle() {
- val in = Bool(INPUT)
- val out = Bool(OUTPUT)
- }
+ val io = IO(new Bundle() {
+ val in = Input(Bool())
+ val out = Output(Bool())
+ })
}
class BlackBoxPassthrough extends BlackBox {
- val io = new Bundle() {
- val in = Bool(INPUT)
- val out = Bool(OUTPUT)
- }
+ val io = IO(new Bundle() {
+ val in = Input(Bool())
+ val out = Output(Bool())
+ })
}
class BlackBoxRegister extends BlackBox {
- val io = new Bundle() {
- val clock = Clock().asInput
- val in = Bool(INPUT)
- val out = Bool(OUTPUT)
- }
+ val io = IO(new Bundle() {
+ val clock = Input(Clock())
+ val in = Input(Bool())
+ val out = Output(Bool())
+ })
}
class BlackBoxTester extends BasicTester {
@@ -84,9 +84,9 @@ class BlackBoxWithClockTester extends BasicTester {
/*
// Must determine how to handle parameterized Verilog
class BlackBoxConstant(value: Int) extends BlackBox {
- val io = new Bundle() {
- val out = UInt(width=log2Up(value)).asOutput
- }
+ val io = IO(new Bundle() {
+ val out = Output(UInt(width=log2Up(value)))
+ })
override val name = s"#(WIDTH=${log2Up(value)},VALUE=$value) "
}
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index d79a2625..58f26c1f 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -13,11 +13,11 @@ class Complex[T <: Data](val re: T, val im: T) extends Bundle {
}
class ComplexAssign(w: Int) extends Module {
- val io = new Bundle {
- val e = new Bool(INPUT)
- val in = new Complex(UInt(width = w), UInt(width = w)).asInput
- val out = new Complex(UInt(width = w), UInt(width = w)).asOutput
- }
+ val io = IO(new Bundle {
+ val e = Input(Bool())
+ val in = Input(new Complex(UInt(width = w), UInt(width = w)))
+ val out = Output(new Complex(UInt(width = w), UInt(width = w)))
+ })
when (io.e) {
val tmp = Wire(new Complex(UInt(width = w), UInt(width = w)))
tmp := io.in
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index dd2f6572..28b00adb 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -8,10 +8,10 @@ import org.scalatest.prop._
import Chisel.testers.BasicTester
class DirectionHaver extends Module {
- val io = new Bundle {
- val in = UInt(INPUT, 32)
- val out = UInt(OUTPUT, 32)
- }
+ val io = IO(new Bundle {
+ val in = Input(UInt(32))
+ val out = Output(UInt(32))
+ })
}
class GoodDirection extends DirectionHaver {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index a1bfffda..edb8c80f 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -8,13 +8,13 @@ import org.scalatest._
import org.scalatest.prop._
class GCD extends Module {
- val io = new Bundle {
- val a = UInt(INPUT, 32)
- val b = UInt(INPUT, 32)
- val e = Bool(INPUT)
- val z = UInt(OUTPUT, 32)
- val v = Bool(OUTPUT)
- }
+ val io = IO(new Bundle {
+ val a = Input(UInt(32))
+ val b = Input(UInt(32))
+ val e = Input(Bool())
+ val z = Output(UInt(32))
+ val v = Output(Bool())
+ })
val x = Reg(UInt(width = 32))
val y = Reg(UInt(width = 32))
when (x > y) { x := x -% y }
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 55b704a0..a321522b 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -5,12 +5,12 @@ import Chisel._
import Chisel.testers.BasicTester
class MemorySearch extends Module {
- val io = new Bundle {
- val target = UInt(INPUT, 4)
- val en = Bool(INPUT)
- val done = Bool(OUTPUT)
- val address = UInt(OUTPUT, 3)
- }
+ val io = IO(new Bundle {
+ val target = Input(UInt(4))
+ val en = Input(Bool())
+ val done = Output(Bool())
+ val address = Output(UInt(3))
+ })
val vals = Array(0, 4, 15, 14, 2, 5, 13)
val index = Reg(init = UInt(0, width = 3))
val elts = Vec(vals.map(UInt(_,4)))
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 49ba13c7..1e5ee798 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -8,11 +8,11 @@ import org.scalatest.prop._
import Chisel.testers.BasicTester
class MulLookup(val w: Int) extends Module {
- val io = new Bundle {
- val x = UInt(INPUT, w)
- val y = UInt(INPUT, w)
- val z = UInt(OUTPUT, 2 * w)
- }
+ val io = IO(new Bundle {
+ val x = Input(UInt(w))
+ val y = Input(UInt(w))
+ val z = Output(UInt(2 * w))
+ })
val tbl = Vec(
for {
i <- 0 until 1 << w
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 999b7d36..1f33f8ab 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -4,11 +4,11 @@ package chiselTests
import Chisel._
class Padder extends Module {
- val io = new Bundle {
- val a = Bits(INPUT, 4)
- val asp = SInt(OUTPUT, 8)
- val aup = UInt(OUTPUT, 8)
- }
+ val io = IO(new Bundle {
+ val a = Input(UInt(4))
+ val asp = Output(SInt(8))
+ val aup = Output(UInt(8))
+ })
io.asp := io.a.asSInt
io.aup := io.a.asUInt
}
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index ac799c8a..46e5dc23 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -5,13 +5,13 @@ import scala.collection.mutable.Stack
import Chisel._
class ChiselStack(val depth: Int) extends Module {
- val io = new Bundle {
- val push = Bool(INPUT)
- val pop = Bool(INPUT)
- val en = Bool(INPUT)
- val dataIn = UInt(INPUT, 32)
- val dataOut = UInt(OUTPUT, 32)
- }
+ val io = IO(new Bundle {
+ val push = Input(Bool())
+ val pop = Input(Bool())
+ val en = Input(Bool())
+ val dataIn = Input(UInt(32))
+ val dataOut = Output(UInt(32))
+ })
val stack_mem = Mem(depth, UInt(width = 32))
val sp = Reg(init = UInt(0, width = log2Up(depth + 1)))
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index bb0b0f06..4e8506cf 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -6,23 +6,23 @@ import org.scalatest._
import Chisel.testers.BasicTester
class UIntOps extends Module {
- val io = new Bundle {
- val a = UInt(INPUT, 16)
- val b = UInt(INPUT, 16)
- val addout = UInt(OUTPUT, 16)
- val subout = UInt(OUTPUT, 16)
- val timesout = UInt(OUTPUT, 16)
- val divout = UInt(OUTPUT, 16)
- val modout = UInt(OUTPUT, 16)
- val lshiftout = UInt(OUTPUT, 16)
- val rshiftout = UInt(OUTPUT, 16)
- val lessout = Bool(OUTPUT)
- val greatout = Bool(OUTPUT)
- val eqout = Bool(OUTPUT)
- val noteqout = Bool(OUTPUT)
- val lesseqout = Bool(OUTPUT)
- val greateqout = Bool(OUTPUT)
- }
+ val io = IO(new Bundle {
+ val a = Input(UInt(16))
+ val b = Input(UInt(16))
+ val addout = Output(UInt(16))
+ val subout = Output(UInt(16))
+ val timesout = Output(UInt(16))
+ val divout = Output(UInt(16))
+ val modout = Output(UInt(16))
+ val lshiftout = Output(UInt(16))
+ val rshiftout = Output(UInt(16))
+ val lessout = Output(Bool())
+ val greatout = Output(Bool())
+ val eqout = Output(Bool())
+ val noteqout = Output(Bool())
+ val lesseqout = Output(Bool())
+ val greateqout = Output(Bool())
+ })
val a = io.a
val b = io.b
@@ -76,18 +76,18 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) {
*/
class GoodBoolConversion extends Module {
- val io = new Bundle {
- val u = UInt(1, width = 1).asInput
- val b = Bool(OUTPUT)
- }
+ val io = IO(new Bundle {
+ val u = Input(UInt(1))
+ val b = Output(Bool())
+ })
io.b := io.u.toBool
}
class BadBoolConversion extends Module {
- val io = new Bundle {
- val u = UInt(1, width = 5).asInput
- val b = Bool(OUTPUT)
- }
+ val io = IO(new Bundle {
+ val u = Input(UInt(width = 5))
+ val b = Output(Bool())
+ })
io.b := io.u.toBool
}
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 99ec66a6..936541c0 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -27,8 +27,8 @@ class Packet extends Bundle {
* The problem does not occur if the Vec is taken out
*/
class VectorPacketIO(n: Int) extends Bundle {
- val ins = Vec(n, new DeqIO(new Packet()))
- val outs = Vec(n, new EnqIO(new Packet()))
+ val ins = Vec(n, DeqIO(new Packet()))
+ val outs = Vec(n, EnqIO(new Packet()))
}
/**
@@ -37,10 +37,11 @@ class VectorPacketIO(n: Int) extends Bundle {
*/
class BrokenVectorPacketModule extends Module {
val n = 4
- val io = new VectorPacketIO(n)
+ val io = IO(new VectorPacketIO(n))
/* the following method of initializing the circuit may change in the future */
- io.outs.foreach(_.init())
+ io.ins.foreach(_.noenq())
+ io.outs.foreach(_.nodeq())
}
class VectorPacketIOUnitTester extends BasicTester {
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 20:13:40 +0000