diff options
| author | Richard Lin | 2017-03-08 17:38:14 -0800 |
|---|---|---|
| committer | GitHub | 2017-03-08 17:38:14 -0800 |
| commit | a290d77ef3e88b200ab61cd41fcd1a1138321b66 (patch) | |
| tree | 3cbabf2a20dc34f9d60a585834f532070bcd5235 /src/test/scala/chiselTests/Risc.scala | |
| parent | 09e95c484e145e2a1b2f0a1aacf549c7354a1eca (diff) | |
Deprecate old Reg with nulls constructor (#455)
Diffstat (limited to 'src/test/scala/chiselTests/Risc.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Risc.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index 0d03ff65..07efb7dc 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -17,7 +17,7 @@ class Risc extends Module { val memSize = 256 val file = Mem(memSize, Bits(32.W)) val code = Mem(memSize, Bits(32.W)) - val pc = Reg(init=0.U(8.W)) + val pc = RegInit(0.U(8.W)) val add_op :: imm_op :: Nil = Enum(2) |