diff options
| author | Jim Lawson | 2016-10-06 11:15:08 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-10-06 11:15:08 -0700 |
| commit | d9e46d06522102634b04a187d5e89fe84b94678a (patch) | |
| tree | 3f44fc56acc334c1ffa7340583b29ad44ff8740b /src/test/scala/chiselTests/MultiAssign.scala | |
| parent | f98171296f821034cf66ace070bcf179183e833d (diff) | |
| parent | 7aea39d4deac62d5477904f4bf4381c3482c41d0 (diff) | |
Merge branch 'master' into buildinfo
Diffstat (limited to 'src/test/scala/chiselTests/MultiAssign.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiAssign.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index fa4c4898..397ea4c2 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -9,7 +9,8 @@ import chisel3.testers.BasicTester import chisel3.util._ class LastAssignTester() extends BasicTester { - val cnt = Counter(2) + val countOnClockCycles = Bool(true) + val (cnt, wrap) = Counter(countOnClockCycles,2) val test = Wire(UInt.width(4)) assert(test === 7.U) // allow read references before assign references @@ -20,7 +21,7 @@ class LastAssignTester() extends BasicTester { test := 7.U assert(test === 7.U) // this obviously should work - when(cnt.value === 1.U) { + when(cnt === 1.U) { stop() } } |
