Merge branch 'master' into buildinfo

4 files changed, 23 insertions, 4 deletions

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 83077544..57ceff3f 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -22,6 +22,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     val requireIOWrap = false
     val dontTryConnectionsSwapped = true
     val dontAssumeDirectionality = true
+    val deprecateOldDirectionMethods = true
+    val checkSynthesizable = true
   }
 
   class SmallBundle extends Bundle {
@@ -265,6 +267,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
         val requireIOWrap = false
         val dontTryConnectionsSwapped = true
         val dontAssumeDirectionality = true
+        val deprecateOldDirectionMethods = false
+        val checkSynthesizable = true
       }
 
     }
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index 0a1f31cc..c5a23f82 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -11,7 +11,7 @@ import chisel3.util._
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
-    new Complex(re.chiselCloneType, im.chiselCloneType).asInstanceOf[this.type]
+    new Complex(re.cloneType, im.cloneType).asInstanceOf[this.type]
 }
 
 class ComplexAssign(w: Int) extends Module {
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index 7bf3dded..552fe776 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -3,6 +3,8 @@
 package chiselTests
 
 import chisel3._
+import chisel3.core.Binding.BindingException
+import org.scalatest._
 
 class IOCSimpleIO extends Bundle {
   val in  = Input(UInt(width=32))
@@ -33,7 +35,7 @@ class IOCModuleWire extends Module {
   io.out := inc.out
 }
 
-class IOCompatibilitySpec extends ChiselPropSpec {
+class IOCompatibilitySpec extends ChiselPropSpec with Matchers {
 
   property("IOCModuleVec should elaborate") {
     elaborate { new IOCModuleVec(2) }
@@ -42,4 +44,16 @@ class IOCompatibilitySpec extends ChiselPropSpec {
   property("IOCModuleWire should elaborate") {
     elaborate { new IOCModuleWire }
   }
+
+
+  class IOUnwrapped extends Module {
+    val io = new IOCSimpleIO
+    io.out := io.in
+  }
+
+  property("Unwrapped IO should generate an exception") {
+    a [BindingException] should be thrownBy {
+      elaborate(new IOUnwrapped)
+    }
+  }
 }
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index fa4c4898..397ea4c2 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -9,7 +9,8 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 
 class LastAssignTester() extends BasicTester {
-  val cnt = Counter(2)
+  val countOnClockCycles = Bool(true)
+  val (cnt, wrap) = Counter(countOnClockCycles,2)
 
   val test = Wire(UInt.width(4))
   assert(test === 7.U)  // allow read references before assign references
@@ -20,7 +21,7 @@ class LastAssignTester() extends BasicTester {
   test := 7.U
   assert(test === 7.U)  // this obviously should work
 
-  when(cnt.value === 1.U) {
+  when(cnt === 1.U) {
     stop()
   }
 }