diff options
| author | ducky | 2016-11-17 13:01:03 -0800 |
|---|---|---|
| committer | ducky | 2016-11-21 13:31:12 -0800 |
| commit | 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 (patch) | |
| tree | 7f6f9de04de6eb08878ac46be339fefc2a71395f /src/test/scala/chiselTests/MultiAssign.scala | |
| parent | cd904da0aa0e96ba679906a3ee5dbdc068eace48 (diff) | |
Restyle a lot of test code, mainly with regex
Diffstat (limited to 'src/test/scala/chiselTests/MultiAssign.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiAssign.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 397ea4c2..fbe57da5 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -9,10 +9,10 @@ import chisel3.testers.BasicTester import chisel3.util._ class LastAssignTester() extends BasicTester { - val countOnClockCycles = Bool(true) + val countOnClockCycles = true.B val (cnt, wrap) = Counter(countOnClockCycles,2) - val test = Wire(UInt.width(4)) + val test = Wire(UInt(4.W)) assert(test === 7.U) // allow read references before assign references test := 13.U |