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| author | azidar | 2015-11-06 12:24:00 -0800 |
|---|---|---|
| committer | azidar | 2015-11-06 12:24:53 -0800 |
| commit | 89c5d10c81808406b6ae684e1e122d440466280c (patch) | |
| tree | 571153d80523551cdffa3547dba315b5bfab7742 /src/test/scala/chiselTests/Module.scala | |
| parent | beb67ebad0799bc30ecd6b99601ed6aa8f501892 (diff) | |
Fixed bug that created Vec(Reg(...)) instead of Reg(Vec(...))
Diffstat (limited to 'src/test/scala/chiselTests/Module.scala')
0 files changed, 0 insertions, 0 deletions