diff options
| author | Richard Lin | 2017-03-08 17:38:14 -0800 |
|---|---|---|
| committer | GitHub | 2017-03-08 17:38:14 -0800 |
| commit | a290d77ef3e88b200ab61cd41fcd1a1138321b66 (patch) | |
| tree | 3cbabf2a20dc34f9d60a585834f532070bcd5235 /src/test/scala/chiselTests/MemorySearch.scala | |
| parent | 09e95c484e145e2a1b2f0a1aacf549c7354a1eca (diff) | |
Deprecate old Reg with nulls constructor (#455)
Diffstat (limited to 'src/test/scala/chiselTests/MemorySearch.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MemorySearch.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala index 4cbedf58..d36167a4 100644 --- a/src/test/scala/chiselTests/MemorySearch.scala +++ b/src/test/scala/chiselTests/MemorySearch.scala @@ -13,7 +13,7 @@ class MemorySearch extends Module { val address = Output(UInt(3.W)) }) val vals = Array(0, 4, 15, 14, 2, 5, 13) - val index = Reg(init = 0.U(3.W)) + val index = RegInit(0.U(3.W)) val elts = Vec(vals.map(_.asUInt(4.W))) // val elts = Mem(UInt(32.W), 8) TODO ???? val elt = elts(index) |