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authorJim Lawson2016-07-20 14:49:35 -0700
committerJim Lawson2016-07-20 14:49:35 -0700
commit2dce378deda1cc33833eb378c89a1c5415817bae (patch)
treee3bc5361030d63e017d065491e9e7e4cf788fe3c /src/test/scala/chiselTests/MemorySearch.scala
parent28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 (diff)
Distinguish between ?Int.Lit and ?Int.width
Diffstat (limited to 'src/test/scala/chiselTests/MemorySearch.scala')
-rw-r--r--src/test/scala/chiselTests/MemorySearch.scala10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 770be326..e4063532 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -7,21 +7,21 @@ import chisel3.testers.BasicTester
class MemorySearch extends Module {
val io = IO(new Bundle {
- val target = Input(UInt(4))
+ val target = Input(UInt.width(4))
val en = Input(Bool())
val done = Output(Bool())
- val address = Output(UInt(3))
+ val address = Output(UInt.width(3))
})
val vals = Array(0, 4, 15, 14, 2, 5, 13)
val index = Reg(init = UInt(0, width = 3))
val elts = Vec(vals.map(UInt(_,4)))
// val elts = Mem(UInt(width = 32), 8) TODO ????
val elt = elts(index)
- val end = !io.en && ((elt === io.target) || (index === UInt(7)))
+ val end = !io.en && ((elt === io.target) || (index === UInt.Lit(7)))
when (io.en) {
- index := UInt(0)
+ index := UInt.Lit(0)
} .elsewhen (!end) {
- index := index +% UInt(1)
+ index := index +% UInt.Lit(1)
}
io.done := end
io.address := index