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authorJim Lawson2016-09-29 11:44:09 -0700
committerJim Lawson2016-09-29 11:44:09 -0700
commiteb5e5dc30019be342b7a0534b425bf33b7984ce3 (patch)
tree1f04fd7157a17cc45fe1ff0835500d93809809fd /src/test/scala/chiselTests/IOCompatibility.scala
parent12a651513541d6c96e3b709b424d5d3384179076 (diff)
Massive rename of CompileOptions.
Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports. NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence). We should really thread the CompileOptions through the macro system so the client's implicits are used.
Diffstat (limited to 'src/test/scala/chiselTests/IOCompatibility.scala')
-rw-r--r--src/test/scala/chiselTests/IOCompatibility.scala17
1 files changed, 8 insertions, 9 deletions
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index d100df2b..7bf3dded 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -3,23 +3,22 @@
package chiselTests
import chisel3._
-import chisel3.NotStrict.CompileOptions
class IOCSimpleIO extends Bundle {
- val in = UInt(INPUT, 32)
- val out = UInt(OUTPUT, 32)
+ val in = Input(UInt(width=32))
+ val out = Output(UInt(width=32))
}
class IOCPlusOne extends Module {
- val io = new IOCSimpleIO
+ val io = IO(new IOCSimpleIO)
io.out := io.in + UInt(1)
}
class IOCModuleVec(val n: Int) extends Module {
- val io = new Bundle {
- val ins = Vec(n, UInt(INPUT, 32))
- val outs = Vec(n, UInt(OUTPUT, 32))
- }
+ val io = IO(new Bundle {
+ val ins = Vec(n, Input(UInt(width=32)))
+ val outs = Vec(n, Output(UInt(width=32)))
+ })
val pluses = Vec.fill(n){ Module(new IOCPlusOne).io }
for (i <- 0 until n) {
pluses(i).in := io.ins(i)
@@ -28,7 +27,7 @@ class IOCModuleVec(val n: Int) extends Module {
}
class IOCModuleWire extends Module {
- val io = new IOCSimpleIO
+ val io = IO(new IOCSimpleIO)
val inc = Wire(Module(new IOCPlusOne).io.chiselCloneType)
inc.in := io.in
io.out := inc.out