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authorJim Lawson2016-10-06 08:57:10 -0700
committerJim Lawson2016-10-06 08:57:10 -0700
commit82625071405672eb4a19363d6f73f359ac28a7f5 (patch)
treedee5beff0e7333fa86c1cdcdb79c0d111114b8c9 /src/test/scala/chiselTests/EnableShiftRegister.scala
parentb7c6e0d1a2098b545938a5a8dfce2b1d9294532f (diff)
parent7de30c2b893a3f24d43f2e131557430eb64f6bc8 (diff)
Merge branch 'master' into tobits-deprecation
Diffstat (limited to 'src/test/scala/chiselTests/EnableShiftRegister.scala')
-rw-r--r--src/test/scala/chiselTests/EnableShiftRegister.scala14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 6600df2a..5f3e0dd1 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -1,15 +1,15 @@
// See LICENSE for license details.
package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
class EnableShiftRegister extends Module {
- val io = new Bundle {
- val in = UInt(INPUT, 4)
- val shift = Bool(INPUT)
- val out = UInt(OUTPUT, 4)
- }
+ val io = IO(new Bundle {
+ val in = Input(UInt.width(4))
+ val shift = Input(Bool())
+ val out = Output(UInt.width(4))
+ })
val r0 = Reg(init = UInt(0, 4))
val r1 = Reg(init = UInt(0, 4))
val r2 = Reg(init = UInt(0, 4))