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authorAlbert Magyar2020-07-20 12:11:44 -0700
committerAlbert Magyar2020-07-21 13:06:53 -0700
commit7e9f424fb7dcd11c894ceb9f6f049fd9eda80632 (patch)
tree1fa15e357d0af7b82316fa2ee659e2e98118488c /src/test/scala/chiselTests/EnableShiftRegister.scala
parent4a0e828cfe76e0d3bd6c4a0cc593589fe74ed0ba (diff)
Delete outdated scalastyle configuration comments from source
Diffstat (limited to 'src/test/scala/chiselTests/EnableShiftRegister.scala')
-rw-r--r--src/test/scala/chiselTests/EnableShiftRegister.scala4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 5f023df8..fd3249fd 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -23,14 +23,13 @@ class EnableShiftRegister extends Module {
io.out := r3
}
-// scalastyle:off regex
/*
class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
val reg = Array.fill(4){ 0 }
for (t <- 0 until 16) {
val in = rnd.nextInt(16)
val shift = rnd.nextInt(2)
- println("SHIFT " + shift + " IN " + in) // scalastyle:ignore regex
+ println("SHIFT " + shift + " IN " + in)
poke(c.io.in, in)
poke(c.io.shift, shift)
step(1)
@@ -43,7 +42,6 @@ class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
}
}
*/
-// scalastyle:on regex
class EnableShiftRegisterSpec extends ChiselPropSpec {