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authorJim Lawson2016-07-20 14:49:35 -0700
committerJim Lawson2016-07-20 14:49:35 -0700
commit2dce378deda1cc33833eb378c89a1c5415817bae (patch)
treee3bc5361030d63e017d065491e9e7e4cf788fe3c /src/test/scala/chiselTests/Direction.scala
parent28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 (diff)
Distinguish between ?Int.Lit and ?Int.width
Diffstat (limited to 'src/test/scala/chiselTests/Direction.scala')
-rw-r--r--src/test/scala/chiselTests/Direction.scala8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 682103f7..e22e120b 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -9,17 +9,17 @@ import chisel3.testers.BasicTester
class DirectionHaver extends Module {
val io = IO(new Bundle {
- val in = Input(UInt(32))
- val out = Output(UInt(32))
+ val in = Input(UInt.width(32))
+ val out = Output(UInt.width(32))
})
}
class GoodDirection extends DirectionHaver {
- io.out := UInt(0)
+ io.out := UInt.Lit(0)
}
class BadDirection extends DirectionHaver {
- io.in := UInt(0)
+ io.in := UInt.Lit(0)
}
class DirectionSpec extends ChiselPropSpec {