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authorRichard Lin2017-07-28 14:45:09 -0700
committerAdam Izraelevitz2017-07-28 14:45:09 -0700
commit004938693112b2be268b0ee8d91874ba2d993ec3 (patch)
treedcacd98e6a66648f45f4d8aa5a3d5e351fe512ca /src/test/scala/chiselTests/Direction.scala
parent2666b809a8964a3ec396714c36bd54469e943516 (diff)
Black box top-level IO fix (#655)
Diffstat (limited to 'src/test/scala/chiselTests/Direction.scala')
-rw-r--r--src/test/scala/chiselTests/Direction.scala10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 9b353840..49d0ab77 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -36,6 +36,12 @@ class BadSubDirection extends DirectionHaver {
io.inBundle.out := 0.U
}
+class TopDirectionOutput extends Module {
+ val io = IO(Output(new DirectionedBundle))
+ io.in := 42.U
+ io.out := 117.U
+}
+
class DirectionSpec extends ChiselPropSpec with Matchers {
//TODO: In Chisel3 these are actually FIRRTL errors. Remove from tests?
@@ -52,4 +58,8 @@ class DirectionSpec extends ChiselPropSpec with Matchers {
elaborate(new BadSubDirection)
}
}
+
+ property("Top-level forced outputs should be assignable") {
+ elaborate(new TopDirectionOutput)
+ }
}