diff options
| author | Richard Lin | 2017-07-28 14:45:09 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2017-07-28 14:45:09 -0700 |
| commit | 004938693112b2be268b0ee8d91874ba2d993ec3 (patch) | |
| tree | dcacd98e6a66648f45f4d8aa5a3d5e351fe512ca /src/test/scala/chiselTests | |
| parent | 2666b809a8964a3ec396714c36bd54469e943516 (diff) | |
Black box top-level IO fix (#655)
Diffstat (limited to 'src/test/scala/chiselTests')
| -rw-r--r-- | src/test/scala/chiselTests/BlackBox.scala | 20 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/Direction.scala | 10 |
2 files changed, 30 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index 983039c5..27895a54 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -25,6 +25,14 @@ class BlackBoxPassthrough extends BlackBox { }) } +// Test Flip on top-level IO +class BlackBoxPassthrough2 extends BlackBox { + val io = IO(Flipped(new Bundle() { + val in = Output(Bool()) + val out = Input(Bool()) + })) +} + class BlackBoxRegister extends BlackBox { val io = IO(new Bundle() { val clock = Input(Clock()) @@ -45,6 +53,14 @@ class BlackBoxTester extends BasicTester { stop() } +class BlackBoxFlipTester extends BasicTester { + val blackBox = Module(new BlackBoxPassthrough2) + + blackBox.io.in := 1.U + assert(blackBox.io.out === 1.U) + stop() +} + /** Instantiate multiple BlackBoxes with similar interfaces but different * functionality. Used to detect failures in BlackBox naming and module * deduplication. @@ -140,6 +156,10 @@ class BlackBoxSpec extends ChiselFlatSpec { assertTesterPasses({ new BlackBoxTester }, Seq("/chisel3/BlackBoxTest.v")) } + "A BlackBoxed with flipped IO" should "work" in { + assertTesterPasses({ new BlackBoxFlipTester }, + Seq("/chisel3/BlackBoxTest.v")) + } "Multiple BlackBoxes" should "work" in { assertTesterPasses({ new MultiBlackBoxTester }, Seq("/chisel3/BlackBoxTest.v")) diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index 9b353840..49d0ab77 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -36,6 +36,12 @@ class BadSubDirection extends DirectionHaver { io.inBundle.out := 0.U } +class TopDirectionOutput extends Module { + val io = IO(Output(new DirectionedBundle)) + io.in := 42.U + io.out := 117.U +} + class DirectionSpec extends ChiselPropSpec with Matchers { //TODO: In Chisel3 these are actually FIRRTL errors. Remove from tests? @@ -52,4 +58,8 @@ class DirectionSpec extends ChiselPropSpec with Matchers { elaborate(new BadSubDirection) } } + + property("Top-level forced outputs should be assignable") { + elaborate(new TopDirectionOutput) + } } |
