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authorJack Koenig2022-01-10 10:39:52 -0800
committerJack Koenig2022-01-10 15:53:55 -0800
commit3131c0daad41dea78bede4517669e376c41a325a (patch)
tree55baed78a6a01f80ff3952a08233ca553a19964f /src/test/scala/chiselTests/DedupSpec.scala
parentdd36f97a82746cec0b25b94651581fe799e24579 (diff)
Apply scalafmt
Command: sbt scalafmtAll
Diffstat (limited to 'src/test/scala/chiselTests/DedupSpec.scala')
-rw-r--r--src/test/scala/chiselTests/DedupSpec.scala6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/DedupSpec.scala b/src/test/scala/chiselTests/DedupSpec.scala
index 61f2995a..f2f2ed45 100644
--- a/src/test/scala/chiselTests/DedupSpec.scala
+++ b/src/test/scala/chiselTests/DedupSpec.scala
@@ -65,11 +65,10 @@ class SharedConstantValDedupTop extends Module {
io.out := inst0.io.out + inst1.io.out
}
-
class DedupSpec extends ChiselFlatSpec {
private val ModuleRegex = """\s*module\s+(\w+)\b.*""".r
def countModules(verilog: String): Int =
- (verilog split "\n" collect { case ModuleRegex(name) => name }).size
+ (verilog.split("\n").collect { case ModuleRegex(name) => name }).size
"Deduplication" should "occur" in {
assert(countModules(compile { new DedupQueues(4) }) === 2)
@@ -80,7 +79,6 @@ class DedupSpec extends ChiselFlatSpec {
}
it should "dedup modules that share a literal" in {
- assert(countModules(compile { new SharedConstantValDedupTop }) === 2)
+ assert(countModules(compile { new SharedConstantValDedupTop }) === 2)
}
}
-