From 3131c0daad41dea78bede4517669e376c41a325a Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Mon, 10 Jan 2022 10:39:52 -0800
Subject: Apply scalafmt

Command:
sbt scalafmtAll
---
 src/test/scala/chiselTests/DedupSpec.scala | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

(limited to 'src/test/scala/chiselTests/DedupSpec.scala')

diff --git a/src/test/scala/chiselTests/DedupSpec.scala b/src/test/scala/chiselTests/DedupSpec.scala
index 61f2995a..f2f2ed45 100644
--- a/src/test/scala/chiselTests/DedupSpec.scala
+++ b/src/test/scala/chiselTests/DedupSpec.scala
@@ -65,11 +65,10 @@ class SharedConstantValDedupTop extends Module {
   io.out := inst0.io.out + inst1.io.out
 }
 
-
 class DedupSpec extends ChiselFlatSpec {
   private val ModuleRegex = """\s*module\s+(\w+)\b.*""".r
   def countModules(verilog: String): Int =
-    (verilog split "\n"  collect { case ModuleRegex(name) => name }).size
+    (verilog.split("\n").collect { case ModuleRegex(name) => name }).size
 
   "Deduplication" should "occur" in {
     assert(countModules(compile { new DedupQueues(4) }) === 2)
@@ -80,7 +79,6 @@ class DedupSpec extends ChiselFlatSpec {
   }
 
   it should "dedup modules that share a literal" in {
-    assert(countModules(compile { new SharedConstantValDedupTop  }) === 2)
+    assert(countModules(compile { new SharedConstantValDedupTop }) === 2)
   }
 }
-
-- 
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