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authorJim Lawson2016-07-20 14:49:35 -0700
committerJim Lawson2016-07-20 14:49:35 -0700
commit2dce378deda1cc33833eb378c89a1c5415817bae (patch)
treee3bc5361030d63e017d065491e9e7e4cf788fe3c /src/test/scala/chiselTests/Decoder.scala
parent28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 (diff)
Distinguish between ?Int.Lit and ?Int.width
Diffstat (limited to 'src/test/scala/chiselTests/Decoder.scala')
-rw-r--r--src/test/scala/chiselTests/Decoder.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index 4a872245..ee892fc5 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -12,7 +12,7 @@ import chisel3.util._
class Decoder(bitpats: List[String]) extends Module {
val io = IO(new Bundle {
- val inst = Input(UInt(32))
+ val inst = Input(UInt.width(32))
val matched = Output(Bool())
})
io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_)
@@ -24,7 +24,7 @@ class DecoderTester(pairs: List[(String, String)]) extends BasicTester {
val dut = Module(new Decoder(bitpats))
dut.io.inst := Vec(insts.map(UInt(_)))(cnt)
when(!dut.io.matched) {
- assert(cnt === UInt(0))
+ assert(cnt === UInt.Lit(0))
stop()
}
when(wrap) {