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authorJim Lawson2016-06-21 10:13:51 -0700
committerJim Lawson2016-06-21 10:13:51 -0700
commit083610b2faa456dfccc4365dd115565d36e522fa (patch)
tree40df9237ddc8789f24d924c0cfa63a066fcc1f1c /src/test/scala/chiselTests/ComplexAssign.scala
parentd675043717593fb7e96fb0f1952debbeb7f20a57 (diff)
Most of the remaining tests with Module, IO wrapping.
Diffstat (limited to 'src/test/scala/chiselTests/ComplexAssign.scala')
-rw-r--r--src/test/scala/chiselTests/ComplexAssign.scala10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index d79a2625..58f26c1f 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -13,11 +13,11 @@ class Complex[T <: Data](val re: T, val im: T) extends Bundle {
}
class ComplexAssign(w: Int) extends Module {
- val io = new Bundle {
- val e = new Bool(INPUT)
- val in = new Complex(UInt(width = w), UInt(width = w)).asInput
- val out = new Complex(UInt(width = w), UInt(width = w)).asOutput
- }
+ val io = IO(new Bundle {
+ val e = Input(Bool())
+ val in = Input(new Complex(UInt(width = w), UInt(width = w)))
+ val out = Output(new Complex(UInt(width = w), UInt(width = w)))
+ })
when (io.e) {
val tmp = Wire(new Complex(UInt(width = w), UInt(width = w)))
tmp := io.in