Check whether signals escape their when scopes (#1518)

* Include and check when scoping as part of reg/mem/wire/node bindings

* Allow outdated 'when' behavior of CHIRRTL memory ports with enables

* Extend cross-module / when-visibility checks to all data refs

* Fixes #1512
* Cannot be checked if outside a module context
* E.g. delayed evaluation of printf / assert args

* Add basic test cases for cross-module refs / signals escaping when scopes

* Remove illegal cross-module references from existing tests

1 files changed, 0 insertions, 19 deletions

diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index 183540af..314bf844 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -252,25 +252,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
     ChiselStage.elaborate { new SwappedConnectionModule() }
   }
 
-  "A Module with directionless connections when compiled with the Chisel compatibility package" should "not throw an exception" in {
-
-    class SimpleModule extends Module {
-      val io = new Bundle {
-        val in = (UInt(width = 3)).asInput
-        val out = (UInt(width = 4)).asOutput
-      }
-      val noDir = Wire(UInt(width = 3))
-    }
-
-    class DirectionLessConnectionModule extends SimpleModule {
-      val a = UInt(0, width = 3)
-      val b = Wire(UInt(width = 3))
-      val child = Module(new SimpleModule)
-      b := child.noDir
-    }
-    ChiselStage.elaborate { new DirectionLessConnectionModule() }
-  }
-
   "Vec ports" should "give default directions to children so they can be used in chisel3.util" in {
     import Chisel._
     ChiselStage.elaborate(new Module {