Check whether signals escape their when scopes (#1518)

* Include and check when scoping as part of reg/mem/wire/node bindings

* Allow outdated 'when' behavior of CHIRRTL memory ports with enables

* Extend cross-module / when-visibility checks to all data refs

* Fixes #1512
* Cannot be checked if outside a module context
* E.g. delayed evaluation of printf / assert args

* Add basic test cases for cross-module refs / signals escaping when scopes

* Remove illegal cross-module references from existing tests

3 files changed, 74 insertions, 38 deletions

diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index 183540af..314bf844 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -252,25 +252,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
     ChiselStage.elaborate { new SwappedConnectionModule() }
   }
 
-  "A Module with directionless connections when compiled with the Chisel compatibility package" should "not throw an exception" in {
-
-    class SimpleModule extends Module {
-      val io = new Bundle {
-        val in = (UInt(width = 3)).asInput
-        val out = (UInt(width = 4)).asOutput
-      }
-      val noDir = Wire(UInt(width = 3))
-    }
-
-    class DirectionLessConnectionModule extends SimpleModule {
-      val a = UInt(0, width = 3)
-      val b = Wire(UInt(width = 3))
-      val child = Module(new SimpleModule)
-      b := child.noDir
-    }
-    ChiselStage.elaborate { new DirectionLessConnectionModule() }
-  }
-
   "Vec ports" should "give default directions to children so they can be used in chisel3.util" in {
     import Chisel._
     ChiselStage.elaborate(new Module {
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 092e6f11..120a6bf3 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -165,23 +165,4 @@ class CompileOptionsSpec extends ChiselFlatSpec with Utils {
     }
   }
 
-  "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
-
-    class SimpleModule extends Module {
-      val io = IO(new Bundle {
-        val in = Input(UInt(3.W))
-        val out = Output(UInt(4.W))
-      })
-      val noDir = Wire(UInt(3.W))
-    }
-
-    class DirectionLessConnectionModule extends SimpleModule {
-      val a = 0.U(3.W)
-      val b = Wire(UInt(3.W))
-      val child = Module(new SimpleModule)
-      b := child.noDir
-    }
-    ChiselStage.elaborate { new DirectionLessConnectionModule() }
-  }
 }
diff --git a/src/test/scala/chiselTests/IllegalRefSpec.scala b/src/test/scala/chiselTests/IllegalRefSpec.scala
new file mode 100644
index 00000000..6f6b1a65
--- /dev/null
+++ b/src/test/scala/chiselTests/IllegalRefSpec.scala
@@ -0,0 +1,74 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+import chisel3.stage.ChiselStage
+
+object IllegalRefSpec {
+  class IllegalRefInner extends RawModule {
+    val io = IO(new Bundle {
+      val i = Input(Bool())
+      val o = Output(Bool())
+    })
+    val x = io.i & io.i
+    io.o := io.i
+  }
+
+  class IllegalRefOuter(useConnect: Boolean) extends RawModule {
+    val io = IO(new Bundle {
+      val a = Input(Bool())
+      val b = Input(Bool())
+      val out = Output(Bool())
+    })
+
+    val inst = Module(new IllegalRefInner)
+    io.out := inst.io.o
+    inst.io.i := io.a
+    val x = WireInit(io.b)
+    if (useConnect) {
+      val z = WireInit(inst.x) // oops
+    } else {
+      val z = inst.x & inst.x // oops
+    }
+  }
+
+  class CrossWhenConnect(useConnect: Boolean) extends RawModule {
+    val io = IO(new Bundle {
+      val i = Input(Bool())
+      val o = Output(Bool())
+    })
+    private var tmp: Option[Bool] = None
+    when (io.i) {
+      val x = io.i & io.i
+      tmp = Some(x)
+    }
+    if (useConnect) {
+      io.o := tmp.get
+    } else {
+      val z = tmp.get & tmp.get
+      io.o := io.i
+    }
+  }
+}
+
+class IllegalRefSpec extends ChiselFlatSpec with Utils {
+  import IllegalRefSpec._
+
+  val variants = Map("a connect" -> true, "an op" -> false)
+
+  variants.foreach {
+    case (k, v) =>
+      s"Illegal cross-module references in ${k}" should "fail" in {
+        a [ChiselException] should be thrownBy extractCause[ChiselException] {
+          ChiselStage.elaborate { new IllegalRefOuter(v) }
+        }
+      }
+
+      s"Using a signal that has escaped its enclosing when scope in ${k}" should "fail" in {
+        a [ChiselException] should be thrownBy extractCause[ChiselException] {
+          ChiselStage.elaborate { new CrossWhenConnect(v) }
+        }
+      }
+  }
+}