diff options
| author | Schuyler Eldridge | 2020-06-22 20:34:46 -0400 |
|---|---|---|
| committer | GitHub | 2020-06-22 20:34:46 -0400 |
| commit | 9f44b593efe4830aeb56d17f5ed59277a74832f8 (patch) | |
| tree | ac43010dd7fc2a14303497f95e12f2a40bb16d0e /src/test/scala/chiselTests/Clock.scala | |
| parent | d099d01ae6b11d8befdf7b32ab74c3167a552984 (diff) | |
| parent | b5e59895e13550006fd8e951b7e9483de00f82dd (diff) | |
Merge pull request #1481 from freechipsproject/driver-deprecations
Remove Deprecated Usages of chisel3.Driver, CircuitForm
Diffstat (limited to 'src/test/scala/chiselTests/Clock.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Clock.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala index 5dea66dc..4b10d3b4 100644 --- a/src/test/scala/chiselTests/Clock.scala +++ b/src/test/scala/chiselTests/Clock.scala @@ -3,6 +3,7 @@ package chiselTests import chisel3._ +import chisel3.stage.ChiselStage import chisel3.testers.BasicTester class ClockAsUIntTester extends BasicTester { @@ -30,7 +31,7 @@ class ClockSpec extends ChiselPropSpec { } property("Should be able to use withClock in a module with no reset") { - val circuit = Driver.emit { () => new WithClockAndNoReset } + val circuit = (new ChiselStage).emitChirrtl(new WithClockAndNoReset) circuit.contains("reg a : UInt<1>, clock2") should be (true) } } |
