From 6e03f63d525aac0bdf4a59b6fe66a0b4d5a3a25a Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 16 Jun 2020 11:59:15 -0400 Subject: Use ChiselStage in Tests This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily involves removing usages of deprecated methods including: - Remove usages of Driver - Use ChiselStage methods instead of BackendCompilationUtilities methods - Use Dependency API for custom transforms - Use extractCause to unpack StackError Signed-off-by: Schuyler Eldridge --- src/test/scala/chiselTests/Clock.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Clock.scala') diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala index 5dea66dc..4b10d3b4 100644 --- a/src/test/scala/chiselTests/Clock.scala +++ b/src/test/scala/chiselTests/Clock.scala @@ -3,6 +3,7 @@ package chiselTests import chisel3._ +import chisel3.stage.ChiselStage import chisel3.testers.BasicTester class ClockAsUIntTester extends BasicTester { @@ -30,7 +31,7 @@ class ClockSpec extends ChiselPropSpec { } property("Should be able to use withClock in a module with no reset") { - val circuit = Driver.emit { () => new WithClockAndNoReset } + val circuit = (new ChiselStage).emitChirrtl(new WithClockAndNoReset) circuit.contains("reg a : UInt<1>, clock2") should be (true) } } -- cgit v1.2.3