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authorChick Markley2017-01-31 09:49:18 -0800
committerGitHub2017-01-31 09:49:18 -0800
commit632a7166ac1935100cb1d61add3b28d1fd4dc8f4 (patch)
tree221079012cebfff37390f6e330711e6a905ffa8f /src/test/scala/chiselTests/ChiselSpec.scala
parent770c5671744502ba7865a41472972388b2fade2c (diff)
Move blackbox verilog implementations within reach of verilator (#453)
* Move blackbox verilog implementations within reach of verilator Blackbox implementers can annotate the modules with information on where to get the source verilog This API is very lightweight, real work is done in firrtl in companion PR Added some verilog to BlackBoxTest.v resource for testing * if a file named black_box_verilog_files.f exists add a -f black_box_verilog_files.f to the verilog to cpp command
Diffstat (limited to 'src/test/scala/chiselTests/ChiselSpec.scala')
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