Move blackbox verilog implementations within reach of verilator (#453)

* Move blackbox verilog implementations within reach of verilator
Blackbox implementers can annotate the modules with information on where to get the source verilog
This API is very lightweight, real work is done in firrtl in companion PR
Added some verilog to BlackBoxTest.v resource for testing

* if a file named black_box_verilog_files.f exists add a
-f black_box_verilog_files.f to the verilog to cpp command

1 files changed, 92 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/BlackBoxImpl.scala b/src/test/scala/chiselTests/BlackBoxImpl.scala
new file mode 100644
index 00000000..fed04d2c
--- /dev/null
+++ b/src/test/scala/chiselTests/BlackBoxImpl.scala
@@ -0,0 +1,92 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import java.io.File
+
+import chisel3._
+import chisel3.util.{HasBlackBoxInline, HasBlackBoxResource}
+import firrtl.FirrtlExecutionSuccess
+import org.scalacheck.Test.Failed
+import org.scalatest.{FreeSpec, Matchers, Succeeded}
+
+//scalastyle:off magic.number
+
+class BlackBoxAdd(n : Int) extends HasBlackBoxInline {
+  val io = IO(new Bundle {
+    val in = Input(UInt(16.W))
+    val out = Output(UInt(16.W))
+  })
+
+  //scalastyle:off regex
+  setInline("BlackBoxAdd.v",
+    s"""
+      |module BlackBoxAdd(
+      |    input  [15:0] in,
+      |    output [15:0] out
+      |);
+      |  assign out = in + $n;
+      |endmodule
+    """.stripMargin)
+}
+
+class UsesBlackBoxAddViaInline extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(16.W))
+    val out = Output(UInt(16.W))
+  })
+
+  val blackBoxAdd = Module(new BlackBoxAdd(5))
+  blackBoxAdd.io.in := io.in
+  io.out := blackBoxAdd.io.out
+}
+
+class BlackBoxMinus extends HasBlackBoxResource {
+  val io = IO(new Bundle {
+    val in1 = Input(UInt(16.W))
+    val in2 = Input(UInt(16.W))
+    val out = Output(UInt(16.W))
+  })
+  setResource("/BlackBoxTest.v")
+}
+
+class UsesBlackBoxMinusViaResource extends Module {
+  val io = IO(new Bundle {
+    val in1 = Input(UInt(16.W))
+    val in2 = Input(UInt(16.W))
+    val out = Output(UInt(16.W))
+  })
+
+  val mod0 = Module(new BlackBoxMinus)
+
+  mod0.io.in1 := io.in1
+  mod0.io.in2 := io.in2
+  io.out := mod0.io.out
+}
+
+class BlackBoxImplSpec extends FreeSpec with Matchers {
+  "BlackBox can have verilator source implementation" - {
+    "Implementations can be contained in-line" in {
+      Driver.execute(Array("-X", "verilog"), () => new UsesBlackBoxAddViaInline) match {
+        case ChiselExecutionSucccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
+          val verilogOutput = new File("./BlackBoxAdd.v")
+          verilogOutput.exists() should be (true)
+          verilogOutput.delete()
+          Succeeded
+        case _ =>
+          Failed
+      }
+    }
+    "Implementations can be contained in resource files" in {
+      Driver.execute(Array("-X", "low"), () => new UsesBlackBoxMinusViaResource) match {
+        case ChiselExecutionSucccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
+          val verilogOutput = new File("./BlackBoxTest.v")
+          verilogOutput.exists() should be (true)
+          verilogOutput.delete()
+          Succeeded
+        case _ =>
+          Failed
+      }
+    }
+  }
+}