Emit UInt.-% as tail(sub(x,y),1), not tail(asUInt(sub(x,y)),1)

This is semantically equivalent, but gets rid of a bunch of Firrtl text.
It also gets rid of a bunch of Verilog, because Firrtl is capable of
pattern-matching the new expression into SubWrap.  The effect is that
we now get

    wire [4:0] in;
    wire [4:0] res;
    assign res = 5'h0 - in;

instead of

    wire [4:0] in;
    wire [5:0] _T_40;
    wire [5:0] _T_41;
    wire [4:0] res;
    assign _T_40 = 5'h0 - in;
    assign _T_41 = $unsigned(_T_40);
    assign res = _T_41[4:0];

0 files changed, 0 insertions, 0 deletions