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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala7
1 files changed, 5 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 7e98cf04..b5de1317 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -738,10 +738,10 @@ sealed class UInt private[core] (width: Width) extends Bits(width) with Num[UInt
(this +& that).tail(1)
/** @group SourceInfoTransformMacro */
def do_-& (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
- binop(sourceInfo, SInt((this.width max that.width) + 1), SubOp, that).asUInt
+ (this subtractAsSInt that).asUInt
/** @group SourceInfoTransformMacro */
def do_-% (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
- (this -& that).tail(1)
+ (this subtractAsSInt that).tail(1)
/** Bitwise and operator
*
@@ -913,6 +913,9 @@ sealed class UInt private[core] (width: Width) extends Bits(width) with Num[UInt
compileOptions: CompileOptions): Unit = {
this := that.asUInt
}
+
+ private def subtractAsSInt(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt =
+ binop(sourceInfo, SInt((this.width max that.width) + 1), SubOp, that)
}
// This is currently a factory because both Bits and UInt inherit it.