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| author | Jim Lawson | 2017-02-28 13:32:38 -0800 |
|---|---|---|
| committer | GitHub | 2017-02-28 13:32:38 -0800 |
| commit | 08885d74619328532bc0157ba9cef7f26496b146 (patch) | |
| tree | 53bd3bd7b4d0b27256700f70b689013a4484674f /src/test/scala/chiselTests/ChiselSpec.scala | |
| parent | cae110e06d7dfb206e6d50565ee25221b8c6d0a5 (diff) | |
Use test_run_dir for more tests. (#534)
* Use test_run_dir for more tests.
* Use official option and DRY.
Make "test_run_dir" the default for ChiselSpec.
Verify output files are created in DriverSpec tests.
Diffstat (limited to 'src/test/scala/chiselTests/ChiselSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/ChiselSpec.scala | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala index 55d58d77..584f134c 100644 --- a/src/test/scala/chiselTests/ChiselSpec.scala +++ b/src/test/scala/chiselTests/ChiselSpec.scala @@ -9,6 +9,7 @@ import org.scalacheck._ import chisel3._ import chisel3.testers._ import firrtl.{ + CommonOptions, ExecutionOptionsManager, HasFirrtlOptions, FirrtlExecutionSuccess, @@ -35,10 +36,17 @@ trait ChiselRunners extends Assertions { */ def generateFirrtl(t: => Module): String = Driver.emit(() => t) - /** Compiles a Chisel Module to Verilog */ + /** Compiles a Chisel Module to Verilog + * NOTE: This uses the "test_run_dir" as the default directory for generated code. + * @param t the generator for the module + * @return the Verilog code as a string. + */ def compile(t: => Module): String = { val manager = new ExecutionOptionsManager("compile") with HasFirrtlOptions - with HasChiselExecutionOptions + with HasChiselExecutionOptions { + commonOptions = CommonOptions(targetDirName = "test_run_dir") + } + Driver.execute(manager, () => t) match { case ChiselExecutionSuccess(_, _, Some(firrtlExecRes)) => firrtlExecRes match { |
