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authorJim Lawson2016-10-06 08:57:10 -0700
committerJim Lawson2016-10-06 08:57:10 -0700
commit82625071405672eb4a19363d6f73f359ac28a7f5 (patch)
treedee5beff0e7333fa86c1cdcdb79c0d111114b8c9 /src/test/scala/chiselTests/BundleWire.scala
parentb7c6e0d1a2098b545938a5a8dfce2b1d9294532f (diff)
parent7de30c2b893a3f24d43f2e131557430eb64f6bc8 (diff)
Merge branch 'master' into tobits-deprecation
Diffstat (limited to 'src/test/scala/chiselTests/BundleWire.scala')
-rw-r--r--src/test/scala/chiselTests/BundleWire.scala17
1 files changed, 9 insertions, 8 deletions
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 658f5bb9..5b38ff6e 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -1,21 +1,22 @@
// See LICENSE for license details.
package chiselTests
-import Chisel._
+import chisel3._
import org.scalatest._
import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
+//import chisel3.core.ExplicitCompileOptions.Strict
class Coord extends Bundle {
- val x = UInt(width = 32)
- val y = UInt(width = 32)
+ val x = UInt.width( 32)
+ val y = UInt.width( 32)
}
class BundleWire(n: Int) extends Module {
- val io = new Bundle {
- val in = (new Coord).asInput
- val outs = Vec(n, new Coord).asOutput
- }
+ val io = IO(new Bundle {
+ val in = Input(new Coord)
+ val outs = Output(Vec(n, new Coord))
+ })
val coords = Wire(Vec(n, new Coord))
for (i <- 0 until n) {
coords(i) := io.in