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authorJim Lawson2016-07-20 14:49:35 -0700
committerJim Lawson2016-07-20 14:49:35 -0700
commit2dce378deda1cc33833eb378c89a1c5415817bae (patch)
treee3bc5361030d63e017d065491e9e7e4cf788fe3c /src/test/scala/chiselTests/BundleWire.scala
parent28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 (diff)
Distinguish between ?Int.Lit and ?Int.width
Diffstat (limited to 'src/test/scala/chiselTests/BundleWire.scala')
-rw-r--r--src/test/scala/chiselTests/BundleWire.scala8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 029407dd..2f6322b1 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -25,11 +25,11 @@ class BundleWire(n: Int) extends Module {
class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
val dut = Module(new BundleWire(n))
- dut.io.in.x := UInt(x)
- dut.io.in.y := UInt(y)
+ dut.io.in.x := UInt.Lit(x)
+ dut.io.in.y := UInt.Lit(y)
for (elt <- dut.io.outs) {
- assert(elt.x === UInt(x))
- assert(elt.y === UInt(y))
+ assert(elt.x === UInt.Lit(x))
+ assert(elt.y === UInt.Lit(y))
}
stop()
}