summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/BlackBox.scala
diff options
context:
space:
mode:
authorRichard Lin2018-10-03 16:15:37 -0700
committerGitHub2018-10-03 16:15:37 -0700
commitdafdeab614a5106dac4d80e147fdbc2770053e1b (patch)
treeefd4ae2f9b612e55c87227851813afb6644ddd3a /src/test/scala/chiselTests/BlackBox.scala
parentb87e6cf65920832c5a0d908b9862edcccf5cae5d (diff)
Add DataMirror.modulePorts (#901)
Diffstat (limited to 'src/test/scala/chiselTests/BlackBox.scala')
-rw-r--r--src/test/scala/chiselTests/BlackBox.scala8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 27895a54..b45171f4 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -172,4 +172,12 @@ class BlackBoxSpec extends ChiselFlatSpec {
assertTesterPasses({ new BlackBoxWithParamsTester },
Seq("/chisel3/BlackBoxTest.v"))
}
+ "DataMirror.modulePorts" should "work with BlackBox" in {
+ elaborate(new Module {
+ val io = IO(new Bundle { })
+ val m = Module(new BlackBoxPassthrough)
+ assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq(
+ "in" -> m.io.in, "out" -> m.io.out))
+ })
+ }
}