diff options
| author | ducky64 | 2017-11-22 22:26:09 -0800 |
|---|---|---|
| committer | Richard Lin | 2018-01-02 13:41:56 -0800 |
| commit | 48e30fab101c5552c73fc5a76cad3ccc6b38946f (patch) | |
| tree | 318a05ff87cb6948c964de5738aa979c27d278e8 /src/test/scala/chiselTests/AnalogIntegrationSpec.scala | |
| parent | 11c1112661e04094bccfd805e737e0318eb91ebc (diff) | |
Support for inner classes, implicit parameter lists, supertypess
Diffstat (limited to 'src/test/scala/chiselTests/AnalogIntegrationSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/AnalogIntegrationSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala index 952d3872..a3e6e643 100644 --- a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala +++ b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala @@ -19,7 +19,7 @@ class AnalogBlackBoxPort extends Bundle { // This IO can be used for a single BlackBox or to group multiple // Has multiple ports for driving and checking but only one shared bus -class AnalogBlackBoxIO(n: Int) extends Bundle { +class AnalogBlackBoxIO(val n: Int) extends Bundle { require(n > 0) val bus = Analog(32.W) val port = Vec(n, new AnalogBlackBoxPort) |