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authorJim Lawson2015-05-11 13:02:03 -0700
committerJim Lawson2015-07-24 15:50:53 -0700
commit2ae50411cbc5e2cd5fdc9ca4069b9c5f64919bc4 (patch)
treea656e44d86a68a7c53b159fe6c74d328a126126d /src/test/scala/ChiselTests/VecApp.scala
parentb208bfb5691c7b5921dd47d0b599726872acd1cd (diff)
Incorporate chisel3-tests; update Makefile.
Diffstat (limited to 'src/test/scala/ChiselTests/VecApp.scala')
-rw-r--r--src/test/scala/ChiselTests/VecApp.scala22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/test/scala/ChiselTests/VecApp.scala b/src/test/scala/ChiselTests/VecApp.scala
new file mode 100644
index 00000000..c32752d6
--- /dev/null
+++ b/src/test/scala/ChiselTests/VecApp.scala
@@ -0,0 +1,22 @@
+package ChiselTests
+import Chisel._
+
+class VecApp(n: Int, W: Int) extends Module {
+ val io = new Bundle {
+ val a = UInt(INPUT, n)
+ val i = Vec(Bits(INPUT, W), n)
+ // val o = Vec.fill(n){ Bits(OUTPUT, W) }
+ val d = Bits(OUTPUT, W)
+ }
+ // for (j <- 0 until n)
+ // io.o(j) := io.i(j)
+ // val w = Wire(Vec.fill(n){ Bits(width = W) })
+ // w := io.i
+ // io.o := w
+ // io.d := w(io.a)
+ io.d := io.i(io.a)
+ // io.o := io.i
+}
+
+class VecAppTester(c: VecApp) extends Tester(c) {
+}