diff options
| author | Jack Koenig | 2016-12-21 14:33:07 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-02-08 18:00:32 -0800 |
| commit | 66a72ff64c46d8a9fdade77223de62b4dcfe2825 (patch) | |
| tree | 8ff97057072ed7ec1e1c64b3f1db774e2c09f99e /src/test/resources | |
| parent | 132b80edee2fb8e730d3b6f5eb5f36051a819525 (diff) | |
Add Analog type
Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
Diffstat (limited to 'src/test/resources')
| -rw-r--r-- | src/test/resources/AnalogBlackBox.v | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/test/resources/AnalogBlackBox.v b/src/test/resources/AnalogBlackBox.v new file mode 100644 index 00000000..79e74a13 --- /dev/null +++ b/src/test/resources/AnalogBlackBox.v @@ -0,0 +1,27 @@ + +module AnalogReaderBlackBox( + inout [31:0] bus, + output [31:0] out +); + assign bus = 32'dz; + assign out = bus; +endmodule + +module AnalogWriterBlackBox( + inout [31:0] bus, + input [31:0] in +); + assign bus = in; +endmodule + +module AnalogBlackBox #( + parameter index=0 +) ( + inout [31:0] bus, + input port_0_in_valid, + input [31:0] port_0_in_bits, + output [31:0] port_0_out +); + assign port_0_out = bus; + assign bus = (port_0_in_valid)? port_0_in_bits + index : 32'dZ; +endmodule |
