From 66a72ff64c46d8a9fdade77223de62b4dcfe2825 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 21 Dec 2016 14:33:07 -0800
Subject: Add Analog type

Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
---
 src/test/resources/AnalogBlackBox.v | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 src/test/resources/AnalogBlackBox.v

(limited to 'src/test/resources')

diff --git a/src/test/resources/AnalogBlackBox.v b/src/test/resources/AnalogBlackBox.v
new file mode 100644
index 00000000..79e74a13
--- /dev/null
+++ b/src/test/resources/AnalogBlackBox.v
@@ -0,0 +1,27 @@
+
+module AnalogReaderBlackBox(
+  inout [31:0] bus,
+  output [31:0] out
+);
+  assign bus = 32'dz;
+  assign out = bus;
+endmodule
+
+module AnalogWriterBlackBox(
+  inout [31:0] bus,
+  input [31:0] in
+);
+  assign bus = in;
+endmodule
+
+module AnalogBlackBox #(
+  parameter index=0
+) (
+  inout [31:0] bus,
+  input port_0_in_valid,
+  input [31:0] port_0_in_bits,
+  output [31:0] port_0_out
+);
+  assign port_0_out = bus;
+  assign bus = (port_0_in_valid)? port_0_in_bits + index : 32'dZ;
+endmodule
-- 
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