diff options
| author | Edward Wang | 2018-07-30 23:39:26 -0400 |
|---|---|---|
| committer | edwardcwang | 2018-08-22 11:55:38 -0700 |
| commit | adfdebc920530199a3a4473b7a1230088fec3f5e (patch) | |
| tree | 31fde6144ab66e8525a7b6ed29a9346b96dc2526 /src/main | |
| parent | cbad7ea20cd0b5ab7d4dc9d631350e1bc1555ddf (diff) | |
Make MixedVec wire init consistent with VecInit
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/chisel3/util/MixedVec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/MixedVec.scala b/src/main/scala/chisel3/util/MixedVec.scala index 30e5bde8..a687c4cd 100644 --- a/src/main/scala/chisel3/util/MixedVec.scala +++ b/src/main/scala/chisel3/util/MixedVec.scala @@ -8,7 +8,7 @@ import chisel3.internal.naming.chiselName import scala.collection.immutable.ListMap -object MixedVecWireInit { +object MixedVecInit { /** * Construct a new wire with the given bound values. * This is analogous to [[chisel3.core.VecInit]]. |