From adfdebc920530199a3a4473b7a1230088fec3f5e Mon Sep 17 00:00:00 2001
From: Edward Wang
Date: Mon, 30 Jul 2018 23:39:26 -0400
Subject: Make MixedVec wire init consistent with VecInit

---
 src/main/scala/chisel3/util/MixedVec.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/scala/chisel3/util/MixedVec.scala b/src/main/scala/chisel3/util/MixedVec.scala
index 30e5bde8..a687c4cd 100644
--- a/src/main/scala/chisel3/util/MixedVec.scala
+++ b/src/main/scala/chisel3/util/MixedVec.scala
@@ -8,7 +8,7 @@ import chisel3.internal.naming.chiselName
 
 import scala.collection.immutable.ListMap
 
-object MixedVecWireInit {
+object MixedVecInit {
   /**
     * Construct a new wire with the given bound values.
     * This is analogous to [[chisel3.core.VecInit]].
-- 
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