diff options
| author | Jack Koenig | 2021-08-17 18:22:16 -0700 |
|---|---|---|
| committer | GitHub | 2021-08-18 01:22:16 +0000 |
| commit | 7c8a032e7e23902283035d93579b8dc477b32f6a (patch) | |
| tree | 1086c8ebb842500cec2b88b7c7a4d961dca8e964 /src/main | |
| parent | e14bcb145860207a825f780e3d0984e869f605c9 (diff) | |
Revert "remove DefRegInit, change DefReg API with option definition. (#1944)" (#2080)
This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/chisel3/aop/Select.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/chisel3/internal/firrtl/Emitter.scala | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala index 81b4cdab..078422bb 100644 --- a/src/main/scala/chisel3/aop/Select.scala +++ b/src/main/scala/chisel3/aop/Select.scala @@ -101,6 +101,7 @@ object Select { check(module) module._component.get.asInstanceOf[DefModule].commands.collect { case r: DefReg => r.id + case r: DefRegInit => r.id } } diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index daa83db0..47849d91 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -66,7 +66,8 @@ private class Emitter(circuit: Circuit) { val firrtlLine = e match { case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})" case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}" - case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}${ if (e.regInit.isDefined) "with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" else ""}" + case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}" + case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]" case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}" case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" |