diff options
5 files changed, 9 insertions, 7 deletions
diff --git a/core/src/main/scala/chisel3/Reg.scala b/core/src/main/scala/chisel3/Reg.scala index 9cdbf6a1..bd9e5311 100644 --- a/core/src/main/scala/chisel3/Reg.scala +++ b/core/src/main/scala/chisel3/Reg.scala @@ -42,7 +42,7 @@ object Reg { val clock = Node(Builder.forcedClock) reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen())) - pushCommand(DefReg(sourceInfo, reg, clock, None)) + pushCommand(DefReg(sourceInfo, reg, clock)) reg } @@ -176,7 +176,7 @@ object RegInit { reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen())) requireIsHardware(init, "reg initializer") - pushCommand(DefReg(sourceInfo, reg, clock.ref, Some(RegInitIR(reset.ref, init.ref)))) + pushCommand(DefRegInit(sourceInfo, reg, clock.ref, reset.ref, init.ref)) reg } diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala index e8fb197c..8efb2abc 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -117,10 +117,10 @@ private[chisel3] object Converter { Some(fir.DefNode(convert(e.sourceInfo), e.name, expr)) case e @ DefWire(info, id) => Some(fir.DefWire(convert(info), e.name, extractType(id, info))) - case e @ DefReg(info, id, clock, None) => + case e @ DefReg(info, id, clock) => Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info), firrtl.Utils.zero, convert(getRef(id, info), ctx, info))) - case e @ DefReg(info, id, clock, Some(RegInitIR(reset, init))) => + case e @ DefRegInit(info, id, clock, reset, init) => Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info), convert(reset, ctx, info), convert(init, ctx, info))) case e @ DefMemory(info, id, t, size) => diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index a45ae3c2..f8a3cf7f 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -758,8 +758,8 @@ abstract class Definition extends Command { case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition -case class RegInitIR(reset: Arg, init: Arg) -case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg, regInit: Option[RegInitIR]) extends Definition +case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition +case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala index 81b4cdab..078422bb 100644 --- a/src/main/scala/chisel3/aop/Select.scala +++ b/src/main/scala/chisel3/aop/Select.scala @@ -101,6 +101,7 @@ object Select { check(module) module._component.get.asInstanceOf[DefModule].commands.collect { case r: DefReg => r.id + case r: DefRegInit => r.id } } diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index daa83db0..47849d91 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -66,7 +66,8 @@ private class Emitter(circuit: Circuit) { val firrtlLine = e match { case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})" case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}" - case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}${ if (e.regInit.isDefined) "with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" else ""}" + case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}" + case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]" case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}" case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" |