Fix bug where flipping top-level I/O had no effect

The fix is to propagate the flip to the fields in the bundle.

3 files changed, 9 insertions, 7 deletions

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 542d31e7..76e45d35 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -805,7 +805,10 @@ abstract class Module(_clock: Clock = null, _reset: Bool = null) extends HasId {
   private[Chisel] def ref = Builder.globalRefMap(this)
   private[Chisel] def lref = ref
 
-  private def computePorts = io.namedElts.unzip._2
+  private[Chisel] def computePorts = io.namedElts.unzip._2 map { x =>
+    val bundleDir = if (io.isFlip ^ x.isFlip) INPUT else OUTPUT
+    Port(x, if (x.dir == NO_DIR) bundleDir else x.dir)
+  }
 
   private def connectImplicitIOs(): this.type = _parent match {
     case Some(p) =>
diff --git a/src/main/scala/Chisel/Emitter.scala b/src/main/scala/Chisel/Emitter.scala
index 867b2107..80c6adf0 100644
--- a/src/main/scala/Chisel/Emitter.scala
+++ b/src/main/scala/Chisel/Emitter.scala
@@ -3,10 +3,8 @@ package Chisel
 private class Emitter(circuit: Circuit) {
   override def toString = res.toString
 
-  private def emitPort(e: Data): String = {
-    val dir = if (e.isFlip) "input" else "output"
-    s"$dir ${e.getRef.name} : ${e.toType}"
-  }
+  private def emitPort(e: Port): String =
+    s"${e.dir} ${e.id.getRef.name} : ${e.id.toType}"
   private def emit(e: Command, ctx: Component): String = e match {
     case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_+", "+_)})"
     case e: DefWire => s"wire ${e.name} : ${e.id.toType}"
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala
index 97c4ff15..209e9f64 100644
--- a/src/main/scala/Chisel/IR.scala
+++ b/src/main/scala/Chisel/IR.scala
@@ -144,14 +144,15 @@ case class DefRegister(id: Data, clock: Arg, reset: Arg) extends Definition
 case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition
 case class DefSeqMemory(id: Data, size: Int) extends Definition
 case class DefAccessor(id: HasId, source: Alias, direction: Direction, index: Arg) extends Definition
-case class DefInstance(id: Module, ports: Seq[Data]) extends Definition
+case class DefInstance(id: Module, ports: Seq[Port]) extends Definition
 case class WhenBegin(pred: Arg) extends Command
 case class WhenElse() extends Command
 case class WhenEnd() extends Command
 case class Connect(loc: Alias, exp: Arg) extends Command
 case class BulkConnect(loc1: Alias, loc2: Alias) extends Command
 case class ConnectInit(loc: Alias, exp: Arg) extends Command
-case class Component(id: Module, name: String, ports: Seq[Data], commands: Seq[Command]) extends Immediate
+case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Immediate
+case class Port(id: Data, dir: Direction)
 
 case class Circuit(name: String, components: Seq[Component], refMap: RefMap, parameterDump: ParameterDump) {
   def emit = new Emitter(this).toString