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Diffstat (limited to 'src/main/scala/Chisel/Core.scala')
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index 542d31e7..76e45d35 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -805,7 +805,10 @@ abstract class Module(_clock: Clock = null, _reset: Bool = null) extends HasId { private[Chisel] def ref = Builder.globalRefMap(this) private[Chisel] def lref = ref - private def computePorts = io.namedElts.unzip._2 + private[Chisel] def computePorts = io.namedElts.unzip._2 map { x => + val bundleDir = if (io.isFlip ^ x.isFlip) INPUT else OUTPUT + Port(x, if (x.dir == NO_DIR) bundleDir else x.dir) + } private def connectImplicitIOs(): this.type = _parent match { case Some(p) => |