Merge pull request #124 from ucb-bar/fix-assert

Fix assert

2 files changed, 6 insertions, 6 deletions

diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index d96787d1..c832426e 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -71,6 +71,7 @@ trait BackendCompilationUtilities {
         "--trace",
         "-O2",
         "+define+TOP_TYPE=V" + dutFile,
+        s"+define+PRINTF_COND=!$dutFile.reset",
         "-CFLAGS",
         s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
         "-Mdir", dir.toString,
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala
index 4547f48f..c0cdfb3f 100644
--- a/src/main/scala/Chisel/testers/TesterDriver.scala
+++ b/src/main/scala/Chisel/testers/TesterDriver.scala
@@ -30,8 +30,7 @@ object TesterDriver extends BackendCompilationUtilities {
     val target = circuit.name
 
     val path = createTempDirectory(target)
-    val fname = File.createTempFile(target, "", path)
-    val prefix = fname.toString.split("/").last
+    val fname = new File(path, target)
 
     // For now, dump the IR out to a file
     Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir")))
@@ -47,10 +46,10 @@ object TesterDriver extends BackendCompilationUtilities {
     })
 
     // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
-    if ((firrtlToVerilog(prefix, path) #&&
-        verilogToCpp(prefix, path, additionalVFiles, cppHarness) #&&
-        cppToExe(prefix, path)).! == 0) {
-      executeExpectingSuccess(prefix, path)
+    if ((firrtlToVerilog(target, path) #&&
+        verilogToCpp(target, path, additionalVFiles, cppHarness) #&&
+        cppToExe(target, path)).! == 0) {
+      executeExpectingSuccess(target, path)
     } else {
       false
     }