Merge pull request #124 from ucb-bar/fix-assert

Fix assert

4 files changed, 49 insertions, 20 deletions

diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index d96787d1..c832426e 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -71,6 +71,7 @@ trait BackendCompilationUtilities {
         "--trace",
         "-O2",
         "+define+TOP_TYPE=V" + dutFile,
+        s"+define+PRINTF_COND=!$dutFile.reset",
         "-CFLAGS",
         s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
         "-Mdir", dir.toString,
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala
index 4547f48f..c0cdfb3f 100644
--- a/src/main/scala/Chisel/testers/TesterDriver.scala
+++ b/src/main/scala/Chisel/testers/TesterDriver.scala
@@ -30,8 +30,7 @@ object TesterDriver extends BackendCompilationUtilities {
     val target = circuit.name
 
     val path = createTempDirectory(target)
-    val fname = File.createTempFile(target, "", path)
-    val prefix = fname.toString.split("/").last
+    val fname = new File(path, target)
 
     // For now, dump the IR out to a file
     Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir")))
@@ -47,10 +46,10 @@ object TesterDriver extends BackendCompilationUtilities {
     })
 
     // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
-    if ((firrtlToVerilog(prefix, path) #&&
-        verilogToCpp(prefix, path, additionalVFiles, cppHarness) #&&
-        cppToExe(prefix, path)).! == 0) {
-      executeExpectingSuccess(prefix, path)
+    if ((firrtlToVerilog(target, path) #&&
+        verilogToCpp(target, path, additionalVFiles, cppHarness) #&&
+        cppToExe(target, path)).! == 0) {
+      executeExpectingSuccess(target, path)
     } else {
       false
     }
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 54ebf366..24eb8b55 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -8,12 +8,39 @@ import Chisel.testers.BasicTester
 
 class FailingAssertTester() extends BasicTester {
   assert(Bool(false))
-  stop()
+  // Wait to come out of reset
+  val (_, done) = Counter(!reset, 4)
+  when (done) {
+    stop()
+  }
 }
 
 class SucceedingAssertTester() extends BasicTester {
   assert(Bool(true))
-  stop()
+  // Wait to come out of reset
+  val (_, done) = Counter(!reset, 4)
+  when (done) {
+    stop()
+  }
+}
+
+class PipelinedResetModule extends Module {
+  val io = new Bundle { }
+  val a = Reg(init = UInt(0xbeef))
+  val b = Reg(init = UInt(0xbeef))
+  assert(a === b)
+}
+
+// This relies on reset being asserted for 3 or more cycles
+class PipelinedResetTester extends BasicTester {
+  val module = Module(new PipelinedResetModule)
+
+  module.reset := Reg(next = Reg(next = Reg(next = reset)))
+
+  val (_, done) = Counter(!reset, 4)
+  when (done) {
+    stop()
+  }
 }
 
 class AssertSpec extends ChiselFlatSpec {
@@ -23,4 +50,7 @@ class AssertSpec extends ChiselFlatSpec {
   "A succeeding assertion" should "not fail the testbench" in {
     assertTesterPasses{ new SucceedingAssertTester }
   }
+  "An assertion" should "not assert until we come out of reset" in {
+    assertTesterPasses{ new PipelinedResetTester }
+  }
 }
diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index 1a628e6c..b06f4572 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -50,30 +50,29 @@ int main(int argc, char **argv, char **env) {
   def simpleHarnessBackend(make: File => File): (File, String) = {
     val target = "test"
     val path = createTempDirectory(target)
-    val fname = File.createTempFile(target, "", path)
-    val prefix = fname.toString.split("/").last
+    val fname = new File(path, target)
 
     val cppHarness = makeCppHarness(fname)
 
     make(fname)
-    verilogToCpp(prefix, path, Seq(), cppHarness).!
-    cppToExe(prefix, path).!
-    (path, prefix)
+    verilogToCpp(target, path, Seq(), cppHarness).!
+    cppToExe(target, path).!
+    (path, target)
   }
 
   property("Test making trivial verilog harness and executing") {
-    val (path, prefix) = simpleHarnessBackend(makeTrivialVerilog)
+    val (path, target) = simpleHarnessBackend(makeTrivialVerilog)
 
-    assert(executeExpectingSuccess(prefix, path))
+    assert(executeExpectingSuccess(target, path))
   }
 
   property("Test that assertion failues in Verilog are caught") {
-    val (path, prefix) = simpleHarnessBackend(makeFailingVerilog)
+    val (path, target) = simpleHarnessBackend(makeFailingVerilog)
 
-    assert(!executeExpectingSuccess(prefix, path))
-    assert(executeExpectingFailure(prefix, path))
-    assert(executeExpectingFailure(prefix, path, "My specific, expected error message!"))
-    assert(!executeExpectingFailure(prefix, path, "A string that doesn't match any test output"))
+    assert(!executeExpectingSuccess(target, path))
+    assert(executeExpectingFailure(target, path))
+    assert(executeExpectingFailure(target, path, "My specific, expected error message!"))
+    assert(!executeExpectingFailure(target, path, "A string that doesn't match any test output"))
   }
 }