Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)

* Move dontTouch out of experimental package.

* Move RawModule, MultiIOModule out of experimental.

* Respond to comments - Move LagacyModule from experimental to internal.
*NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions.

* Fix up a few more imports.

6 files changed, 6 insertions, 8 deletions

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 158ba65a..1caccfc4 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -3,7 +3,6 @@
 package chisel3
 
 import chisel3.internal.ErrorLog
-import chisel3.experimental.RawModule
 import internal.firrtl._
 import firrtl._
 import firrtl.options.{Phase, PhaseManager, StageError}
diff --git a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
index 74cd62f3..00a17d86 100644
--- a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
+++ b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
@@ -2,9 +2,8 @@
 
 package chisel3.aop.injecting
 
-import chisel3.{Module, ModuleAspect, experimental, withClockAndReset}
+import chisel3.{Module, ModuleAspect, experimental, withClockAndReset, RawModule, MultiIOModule}
 import chisel3.aop._
-import chisel3.experimental.RawModule
 import chisel3.internal.Builder
 import chisel3.internal.firrtl.DefModule
 import chisel3.stage.DesignAnnotation
@@ -36,7 +35,7 @@ case class InjectingAspect[T <: RawModule,
     RunFirrtlTransformAnnotation(new InjectingTransform) +: modules.map { module =>
       val (chiselIR, _) = Builder.build(Module(new ModuleAspect(module) {
         module match {
-          case x: experimental.MultiIOModule => withClockAndReset(x.clock, x.reset) { injection(module) }
+          case x: MultiIOModule => withClockAndReset(x.clock, x.reset) { injection(module) }
           case x: RawModule => injection(module)
         }
       }))
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 24556461..02dfa329 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -300,7 +300,7 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
 
   import chisel3.CompileOptions
   abstract class CompatibilityModule(implicit moduleCompileOptions: CompileOptions)
-      extends chisel3.experimental.LegacyModule {
+      extends chisel3.internal.LegacyModule {
     // This class auto-wraps the Module IO with IO(...), allowing legacy code (where IO(...) wasn't
     // required) to build.
     // Also provides the clock / reset constructors, which were used before withClock happened.
diff --git a/src/main/scala/chisel3/stage/ChiselAnnotations.scala b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
index e722bac2..bfce0e8d 100644
--- a/src/main/scala/chisel3/stage/ChiselAnnotations.scala
+++ b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
@@ -5,7 +5,7 @@ package chisel3.stage
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
 import firrtl.options.{HasShellOptions, OptionsException, ShellOption, Unserializable}
 import chisel3.{ChiselException, Module}
-import chisel3.experimental.RawModule
+import chisel3.RawModule
 import chisel3.internal.Builder
 import chisel3.internal.firrtl.Circuit
 import firrtl.AnnotationSeq
diff --git a/src/main/scala/chisel3/stage/phases/AspectPhase.scala b/src/main/scala/chisel3/stage/phases/AspectPhase.scala
index f8038a2c..8d48e338 100644
--- a/src/main/scala/chisel3/stage/phases/AspectPhase.scala
+++ b/src/main/scala/chisel3/stage/phases/AspectPhase.scala
@@ -3,7 +3,7 @@
 package chisel3.stage.phases
 
 import chisel3.aop.Aspect
-import chisel3.experimental.RawModule
+import chisel3.RawModule
 import chisel3.stage.DesignAnnotation
 import firrtl.AnnotationSeq
 import firrtl.options.Phase
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 36892c11..15b4ab1d 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -6,7 +6,7 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.experimental.{DataMirror, Direction, MultiIOModule, requireIsChiselType}
+import chisel3.experimental.{DataMirror, Direction, requireIsChiselType}
 import chisel3.internal.naming._  // can't use chisel3_ version because of compile order
 
 /** An I/O Bundle containing 'valid' and 'ready' signals that handshake