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authorJim Lawson2016-07-20 13:28:15 -0700
committerJim Lawson2016-07-20 13:28:15 -0700
commit28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 (patch)
tree5d7a077498317c5f2412604380acc43c6b1fc371 /src/main/scala/chisel3
parentf81202b896d30d90075be487895befa009b11733 (diff)
Compile ok.
Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)
Diffstat (limited to 'src/main/scala/chisel3')
-rw-r--r--src/main/scala/chisel3/package.scala8
-rw-r--r--src/main/scala/chisel3/util/BitPat.scala4
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala6
-rw-r--r--src/main/scala/chisel3/util/Valid.scala6
4 files changed, 19 insertions, 5 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 71ec0e92..86fce6a2 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,9 +1,10 @@
+// See LICENSE for license details.
+
package object chisel3 {
import scala.language.experimental.macros
import internal.firrtl.Width
import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
-
import util.BitPat
@@ -87,6 +88,11 @@ package object chisel3 {
implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
def U: UInt = UInt(x, Width())
def S: SInt = SInt(x, Width())
+
+ def asUInt() = UInt(x, Width())
+ def asSInt() = SInt(x, Width())
+ def asUInt(width: Int) = UInt(x, width)
+ def asSInt(width: Int) = SInt(x, width)
}
implicit class fromStringToLiteral(val x: String) extends AnyVal {
def U: UInt = UInt(x)
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 9eb5cf67..3ae192a2 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -75,7 +75,7 @@ object BitPat {
// TODO: Break out of Core? (this doesn't involve FIRRTL generation)
/** Bit patterns are literals with masks, used to represent values with don't
* cares. Equality comparisons will ignore don't care bits (for example,
- * BitPat(0b10?1) === UInt(0b1001) and UInt(0b1011)).
+ * BitPat(0b10?1) === 0b1001.asUInt and 0b1011.asUInt.
*/
sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
def getWidth: Int = width
@@ -83,7 +83,7 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg
def != (that: UInt): Bool = macro SourceInfoTransform.thatArg
- def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value) === (that & UInt(mask))
+ def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = value.asUInt === (that & mask.asUInt)
def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that)
def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that
}
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 4a6b72e9..fb1ee6b9 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -58,7 +58,11 @@ object DecoupledIO {
target.ready := Bool(false)
}
}
-// override def cloneType: this.type = { DeqIO(gen).asInstanceOf[this.type]; }
+// override def cloneType: this.type = {
+// val clone = DeqIO(gen).asInstanceOf[this.type]
+// clone.unBind()
+// clone
+// }
}
object EnqIO {
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 4078a76a..5641f0f2 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -13,7 +13,11 @@ class Valid[+T <: Data](gen: T) extends Bundle
val valid = Output(Bool())
val bits = Output(gen.cloneType)
def fire(dummy: Int = 0): Bool = valid
- override def cloneType: this.type = Valid(gen).asInstanceOf[this.type]
+ override def cloneType: this.type = {
+ val clone = Valid(gen).asInstanceOf[this.type]
+ clone.unBind()
+ clone
+ }
}
/** Adds a valid protocol to any interface */