diff options
| author | Richard Lin | 2016-11-29 16:37:13 -0800 |
|---|---|---|
| committer | GitHub | 2016-11-29 16:37:13 -0800 |
| commit | 7680363982b02f53e9f76f5d5e242e44f17da6f7 (patch) | |
| tree | 1b68e829fa8503440fcc564ea8d26207b7e2fb88 /src/main/scala/chisel3/util | |
| parent | edb19a0559686a471141c74438f677c1e217a298 (diff) | |
Add feature warnings to build, fix feature warnings, fix some documentation (#387)
Diffstat (limited to 'src/main/scala/chisel3/util')
| -rw-r--r-- | src/main/scala/chisel3/util/ImplicitConversions.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 6 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala index c2ba710d..712975a7 100644 --- a/src/main/scala/chisel3/util/ImplicitConversions.scala +++ b/src/main/scala/chisel3/util/ImplicitConversions.scala @@ -4,6 +4,8 @@ package chisel3.util import chisel3._ +import scala.language.implicitConversions + object ImplicitConversions { // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and // UInt.asUInt. diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index 49a6f515..0229b7f8 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -52,10 +52,12 @@ object Pipe class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module { - val io = IO(new Bundle { + class PipeIO extends Bundle { val enq = Input(Valid(gen)) val deq = Output(Valid(gen)) - }) + } + + val io = IO(new PipeIO) io.deq <> Pipe(io.enq, latency) } |
