diff options
| author | Richard Lin | 2016-11-29 16:37:13 -0800 |
|---|---|---|
| committer | GitHub | 2016-11-29 16:37:13 -0800 |
| commit | 7680363982b02f53e9f76f5d5e242e44f17da6f7 (patch) | |
| tree | 1b68e829fa8503440fcc564ea8d26207b7e2fb88 | |
| parent | edb19a0559686a471141c74438f677c1e217a298 (diff) | |
Add feature warnings to build, fix feature warnings, fix some documentation (#387)
| -rw-r--r-- | build.sbt | 2 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/compatibility.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/package.scala | 8 | ||||
| -rw-r--r-- | src/main/scala/chisel3/testers/TesterDriver.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/ImplicitConversions.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 6 |
7 files changed, 15 insertions, 9 deletions
@@ -19,7 +19,7 @@ lazy val commonSettings = Seq ( git.remoteRepo := "git@github.com:ucb-bar/chisel3.git", autoAPIMappings := true, scalaVersion := "2.11.7", - scalacOptions := Seq("-deprecation") + scalacOptions := Seq("-deprecation", "-feature") ) val defaultVersions = Map("firrtl" -> "1.1-SNAPSHOT") diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 17354799..9bbf9d0e 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -225,7 +225,7 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) private[chisel3] lazy val flatten: IndexedSeq[Bits] = (0 until length).flatMap(i => this.apply(i).flatten) - for ((elt, i) <- self zipWithIndex) + for ((elt, i) <- self.zipWithIndex) elt.setRef(this, i) /** Default "pretty-print" implementation diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 4ffd0b86..613385af 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -120,7 +120,7 @@ package object Chisel { // scalastyle:ignore package.object.name */ trait BoolFactory extends chisel3.core.BoolFactory { /** Creates Bool literal. - */ + */ def apply(x: Boolean): Bool = x.B /** Create a UInt with a specified direction and width - compatibility with Chisel2. */ diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index 449f4ea5..e4e64b89 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. package object chisel3 { // scalastyle:ignore package.object.name + import scala.language.implicitConversions + import internal.firrtl.Width import util.BitPat @@ -267,11 +269,11 @@ package object chisel3 { // scalastyle:ignore package.object.name import internal.firrtl.NumericBound /** Specifies a range using mathematical range notation. Variables can be interpolated using - * standard string interpolation syntax. + * standard string interpolation syntax. * @example {{{ * UInt(range"[0, 2)") - * UInt(range"[0, $myInt)") - * UInt(range"[0, ${myInt + 2})") + * UInt(range"[0, \$myInt)") + * UInt(range"[0, \${myInt + 2})") * }}} */ def range(args: Any*): (NumericBound[Int], NumericBound[Int]) = macro chisel3.internal.RangeTransform.apply diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala index 76b9a2e9..83f3c796 100644 --- a/src/main/scala/chisel3/testers/TesterDriver.scala +++ b/src/main/scala/chisel3/testers/TesterDriver.scala @@ -14,7 +14,7 @@ object TesterDriver extends BackendCompilationUtilities { throw new FileNotFoundException(s"Resource '$name'") } val out = new FileOutputStream(file) - Iterator.continually(in.read).takeWhile(-1 !=).foreach(out.write) + Iterator.continually(in.read).takeWhile(-1 != _).foreach(out.write) out.close() } diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala index c2ba710d..712975a7 100644 --- a/src/main/scala/chisel3/util/ImplicitConversions.scala +++ b/src/main/scala/chisel3/util/ImplicitConversions.scala @@ -4,6 +4,8 @@ package chisel3.util import chisel3._ +import scala.language.implicitConversions + object ImplicitConversions { // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and // UInt.asUInt. diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index 49a6f515..0229b7f8 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -52,10 +52,12 @@ object Pipe class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module { - val io = IO(new Bundle { + class PipeIO extends Bundle { val enq = Input(Valid(gen)) val deq = Output(Valid(gen)) - }) + } + + val io = IO(new PipeIO) io.deq <> Pipe(io.enq, latency) } |
