Add partial util files so that it successfully compiles

4 files changed, 9 insertions, 9 deletions

diff --git a/src/main/scala/chisel3/util/experimental/ForceNames.scala b/src/main/scala/chisel3/util/experimental/ForceNames.scala
index 3070a210..39517e02 100644
--- a/src/main/scala/chisel3/util/experimental/ForceNames.scala
+++ b/src/main/scala/chisel3/util/experimental/ForceNames.scala
@@ -28,7 +28,7 @@ object forceName {
     if (!signal.isSynthesizable) Builder.deprecated(s"Using forceName '$name' on non-hardware value $signal")
     annotate(new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl = ForceNameAnnotation(signal.toTarget, name)
-      override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform]
+      override def transformClass: Class[? <: Transform] = classOf[ForceNamesTransform]
     })
     signal
   }
@@ -42,7 +42,7 @@ object forceName {
     if (!signal.isSynthesizable) Builder.deprecated(s"Using forceName on non-hardware value $signal")
     annotate(new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl = ForceNameAnnotation(signal.toTarget, signal.toTarget.ref)
-      override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform]
+      override def transformClass: Class[? <: Transform] = classOf[ForceNamesTransform]
     })
     signal
   }
@@ -57,7 +57,7 @@ object forceName {
         val t = instance.toAbsoluteTarget
         ForceNameAnnotation(t, name)
       }
-      override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform]
+      override def transformClass: Class[? <: Transform] = classOf[ForceNamesTransform]
     })
   }
 
@@ -72,7 +72,7 @@ object forceName {
         val t = instance.toAbsoluteTarget
         ForceNameAnnotation(t, instance.instanceName)
       }
-      override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform]
+      override def transformClass: Class[? <: Transform] = classOf[ForceNamesTransform]
     })
   }
 }
@@ -132,7 +132,7 @@ private object ForceNamesTransform {
           .view
           .map(_.map(_.toTokens).toList)
           .toList
-    allInstancePaths(lookup) _
+    allInstancePaths(lookup)
   }
 
   /** Returns a function which returns all instance paths to a given IsModule
diff --git a/src/main/scala/chisel3/util/experimental/Inline.scala b/src/main/scala/chisel3/util/experimental/Inline.scala
index fd5c6aa5..e9b2cec1 100644
--- a/src/main/scala/chisel3/util/experimental/Inline.scala
+++ b/src/main/scala/chisel3/util/experimental/Inline.scala
@@ -43,7 +43,7 @@ trait InlineInstance { self: BaseModule =>
   Seq(
     new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl:       Annotation = InlineAnnotation(self.toNamed)
-      def transformClass: Class[_ <: Transform] = classOf[InlineInstances]
+      def transformClass: Class[? <: Transform] = classOf[InlineInstances]
     },
     new ChiselAnnotation {
       def toFirrtl: Annotation = NoDedupAnnotation(self.toNamed)
@@ -82,7 +82,7 @@ trait FlattenInstance { self: BaseModule =>
   Seq(
     new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl:       Annotation = FlattenAnnotation(self.toNamed)
-      def transformClass: Class[_ <: Transform] = classOf[Flatten]
+      def transformClass: Class[? <: Transform] = classOf[Flatten]
     },
     new ChiselAnnotation {
       def toFirrtl: Annotation = NoDedupAnnotation(self.toNamed)
diff --git a/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala b/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala
index 26a072f1..9004ef28 100644
--- a/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala
+++ b/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala
@@ -264,7 +264,7 @@ object QMCMinimizer extends Minimizer {
 
       implicants.foreach(_.isPrime = true)
       val cols = (0 to n).reverse.map(b => implicants.filter(b == _.bp.mask.bitCount))
-      val mergeTable = cols.map(c => (0 to n).map(b => collection.mutable.Set(c.filter(b == _.bp.value.bitCount): _*)))
+      val mergeTable = cols.map(c => (0 to n).map(b => collection.mutable.Set(c.filter(b == _.bp.value.bitCount)*)))
 
       // O(n ^ 3)
       for (i <- 0 to n) {
diff --git a/src/main/scala/chisel3/util/experimental/group.scala b/src/main/scala/chisel3/util/experimental/group.scala
index ac687da7..faa086f1 100644
--- a/src/main/scala/chisel3/util/experimental/group.scala
+++ b/src/main/scala/chisel3/util/experimental/group.scala
@@ -58,7 +58,7 @@ object group {
     annotate(new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl = GroupAnnotation(components.map(_.toNamed), newModule, newInstance, outputSuffix, inputSuffix)
 
-      override def transformClass: Class[_ <: Transform] = classOf[GroupComponents]
+      override def transformClass: Class[? <: Transform] = classOf[GroupComponents]
     })
   }
 }