Add partial util files so that it successfully compiles

9 files changed, 20 insertions, 19 deletions

diff --git a/src/main/scala/chisel3/stage/ChiselAnnotations.scala b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
index 318945c8..8972310b 100644
--- a/src/main/scala/chisel3/stage/ChiselAnnotations.scala
+++ b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
@@ -135,7 +135,7 @@ object ChiselGeneratorAnnotation extends HasShellOptions {
   def apply(name: String): ChiselGeneratorAnnotation = {
     val gen = () =>
       try {
-        Class.forName(name).asInstanceOf[Class[_ <: RawModule]].newInstance()
+        Class.forName(name).asInstanceOf[Class[? <: RawModule]].newInstance()
       } catch {
         case e: ClassNotFoundException =>
           throw new OptionsException(s"Unable to locate module '$name'! (Did you misspell it?)", e)
diff --git a/src/main/scala/chisel3/stage/phases/Convert.scala b/src/main/scala/chisel3/stage/phases/Convert.scala
index aeeff246..41ee8226 100644
--- a/src/main/scala/chisel3/stage/phases/Convert.scala
+++ b/src/main/scala/chisel3/stage/phases/Convert.scala
@@ -31,7 +31,7 @@ class Convert extends Phase {
         a.circuit.firrtlAnnotations ++
         a.circuit.annotations.collect {
           case anno: RunFirrtlTransform => anno.transformClass
-        }.distinct.map { c: Class[_ <: Transform] => RunFirrtlTransformAnnotation(c.newInstance()) }
+        }.distinct.map { (c: Class[? <: Transform]) => RunFirrtlTransformAnnotation(c.newInstance()) }
     case a => Some(a)
   }
 
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 4fc4d78c..5a1af691 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -24,14 +24,14 @@ object FillInterleaved {
     *
     * Output data-equivalent to in(size(in)-1) (n times) ## ... ## in(1) (n times) ## in(0) (n times)
     */
-  def apply(@deprecatedName('n, "Chisel 3.5") n: Int, @deprecatedName('in, "Chisel 3.5") in: UInt): UInt =
+  def apply(@deprecatedName(Symbol("n"), "Chisel 3.5") n: Int, @deprecatedName(Symbol("in"), "Chisel 3.5") in: UInt): UInt =
     apply(n, in.asBools)
 
   /** Creates n repetitions of each bit of x in order.
     *
     * Output data-equivalent to in(size(in)-1) (n times) ## ... ## in(1) (n times) ## in(0) (n times)
     */
-  def apply(@deprecatedName('n, "Chisel 3.5") n: Int, @deprecatedName('in, "Chisel 3.5") in: Seq[Bool]): UInt = Cat(
+  def apply(@deprecatedName(Symbol("n"), "Chisel 3.5") n: Int, @deprecatedName(Symbol("in"), "Chisel 3.5") in: Seq[Bool]): UInt = Cat(
     in.map(Fill(n, _)).reverse
   )
 }
@@ -48,9 +48,9 @@ object FillInterleaved {
   * }}}
   */
 object PopCount {
-  def apply(@deprecatedName('in, "Chisel 3.5") in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq)
+  def apply(@deprecatedName(Symbol("in"), "Chisel 3.5") in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq)
 
-  def apply(@deprecatedName('in, "Chisel 3.5") in: Bits): UInt = apply((0 until in.getWidth).map(in(_)))
+  def apply(@deprecatedName(Symbol("in"), "Chisel 3.5") in: Bits): UInt = apply((0 until in.getWidth).map(in(_)))
 }
 
 /** Create repetitions of the input using a tree fanout topology.
@@ -68,7 +68,7 @@ object Fill {
     * Output data-equivalent to x ## x ## ... ## x (n repetitions).
     * @throws java.lang.IllegalArgumentException if `n` is less than zero
     */
-  def apply(@deprecatedName('n, "Chisel 3.5") n: Int, @deprecatedName('x, "Chisel 3.5") x: UInt): UInt = {
+  def apply(@deprecatedName(Symbol("n"), "Chisel 3.5") n: Int, @deprecatedName(Symbol("x"), "Chisel 3.5") x: UInt): UInt = {
     n match {
       case _ if n < 0 => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.")
       case 0          => UInt(0.W)
@@ -114,5 +114,5 @@ object Reverse {
       Cat(doit(in(half - 1, 0), half), doit(in(length - 1, half), length - half))
   }
 
-  def apply(@deprecatedName('in, "Chisel 3.5") in: UInt): UInt = doit(in, in.getWidth)
+  def apply(@deprecatedName(Symbol("in"), "Chisel 3.5") in: UInt): UInt = doit(in, in.getWidth)
 }
diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala
index 3224ec03..4f4c87ca 100644
--- a/src/main/scala/chisel3/util/Cat.scala
+++ b/src/main/scala/chisel3/util/Cat.scala
@@ -19,7 +19,7 @@ object Cat {
   /** Concatenates the argument data elements, in argument order, together. The first argument
     * forms the most significant bits, while the last argument forms the least significant bits.
     */
-  def apply[T <: Bits](@deprecatedName('a, "Chisel 3.5") a: T, @deprecatedName('r, "Chisel 3.5") r: T*): UInt = apply(
+  def apply[T <: Bits](@deprecatedName(Symbol("a"), "Chisel 3.5") a: T, @deprecatedName(Symbol("r"), "Chisel 3.5") r: T*): UInt = apply(
     a :: r.toList
   )
 
@@ -30,5 +30,5 @@ object Cat {
     * Equivalent to r(0) ## r(1) ## ... ## r(n-1).
     * @note This returns a `0.U` if applied to a zero-element `Vec`.
     */
-  def apply[T <: Bits](@deprecatedName('r, "Chisel 3.5") r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse)
+  def apply[T <: Bits](@deprecatedName(Symbol("r"), "Chisel 3.5") r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse)
 }
diff --git a/src/main/scala/chisel3/util/experimental/ForceNames.scala b/src/main/scala/chisel3/util/experimental/ForceNames.scala
index 3070a210..39517e02 100644
--- a/src/main/scala/chisel3/util/experimental/ForceNames.scala
+++ b/src/main/scala/chisel3/util/experimental/ForceNames.scala
@@ -28,7 +28,7 @@ object forceName {
     if (!signal.isSynthesizable) Builder.deprecated(s"Using forceName '$name' on non-hardware value $signal")
     annotate(new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl = ForceNameAnnotation(signal.toTarget, name)
-      override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform]
+      override def transformClass: Class[? <: Transform] = classOf[ForceNamesTransform]
     })
     signal
   }
@@ -42,7 +42,7 @@ object forceName {
     if (!signal.isSynthesizable) Builder.deprecated(s"Using forceName on non-hardware value $signal")
     annotate(new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl = ForceNameAnnotation(signal.toTarget, signal.toTarget.ref)
-      override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform]
+      override def transformClass: Class[? <: Transform] = classOf[ForceNamesTransform]
     })
     signal
   }
@@ -57,7 +57,7 @@ object forceName {
         val t = instance.toAbsoluteTarget
         ForceNameAnnotation(t, name)
       }
-      override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform]
+      override def transformClass: Class[? <: Transform] = classOf[ForceNamesTransform]
     })
   }
 
@@ -72,7 +72,7 @@ object forceName {
         val t = instance.toAbsoluteTarget
         ForceNameAnnotation(t, instance.instanceName)
       }
-      override def transformClass: Class[_ <: Transform] = classOf[ForceNamesTransform]
+      override def transformClass: Class[? <: Transform] = classOf[ForceNamesTransform]
     })
   }
 }
@@ -132,7 +132,7 @@ private object ForceNamesTransform {
           .view
           .map(_.map(_.toTokens).toList)
           .toList
-    allInstancePaths(lookup) _
+    allInstancePaths(lookup)
   }
 
   /** Returns a function which returns all instance paths to a given IsModule
diff --git a/src/main/scala/chisel3/util/experimental/Inline.scala b/src/main/scala/chisel3/util/experimental/Inline.scala
index fd5c6aa5..e9b2cec1 100644
--- a/src/main/scala/chisel3/util/experimental/Inline.scala
+++ b/src/main/scala/chisel3/util/experimental/Inline.scala
@@ -43,7 +43,7 @@ trait InlineInstance { self: BaseModule =>
   Seq(
     new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl:       Annotation = InlineAnnotation(self.toNamed)
-      def transformClass: Class[_ <: Transform] = classOf[InlineInstances]
+      def transformClass: Class[? <: Transform] = classOf[InlineInstances]
     },
     new ChiselAnnotation {
       def toFirrtl: Annotation = NoDedupAnnotation(self.toNamed)
@@ -82,7 +82,7 @@ trait FlattenInstance { self: BaseModule =>
   Seq(
     new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl:       Annotation = FlattenAnnotation(self.toNamed)
-      def transformClass: Class[_ <: Transform] = classOf[Flatten]
+      def transformClass: Class[? <: Transform] = classOf[Flatten]
     },
     new ChiselAnnotation {
       def toFirrtl: Annotation = NoDedupAnnotation(self.toNamed)
diff --git a/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala b/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala
index 26a072f1..9004ef28 100644
--- a/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala
+++ b/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala
@@ -264,7 +264,7 @@ object QMCMinimizer extends Minimizer {
 
       implicants.foreach(_.isPrime = true)
       val cols = (0 to n).reverse.map(b => implicants.filter(b == _.bp.mask.bitCount))
-      val mergeTable = cols.map(c => (0 to n).map(b => collection.mutable.Set(c.filter(b == _.bp.value.bitCount): _*)))
+      val mergeTable = cols.map(c => (0 to n).map(b => collection.mutable.Set(c.filter(b == _.bp.value.bitCount)*)))
 
       // O(n ^ 3)
       for (i <- 0 to n) {
diff --git a/src/main/scala/chisel3/util/experimental/group.scala b/src/main/scala/chisel3/util/experimental/group.scala
index ac687da7..faa086f1 100644
--- a/src/main/scala/chisel3/util/experimental/group.scala
+++ b/src/main/scala/chisel3/util/experimental/group.scala
@@ -58,7 +58,7 @@ object group {
     annotate(new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl = GroupAnnotation(components.map(_.toNamed), newModule, newInstance, outputSuffix, inputSuffix)
 
-      override def transformClass: Class[_ <: Transform] = classOf[GroupComponents]
+      override def transformClass: Class[? <: Transform] = classOf[GroupComponents]
     })
   }
 }
diff --git a/src/main/scala/chisel3/verilog.scala b/src/main/scala/chisel3/verilog.scala
index c301ff98..a29dd0c5 100644
--- a/src/main/scala/chisel3/verilog.scala
+++ b/src/main/scala/chisel3/verilog.scala
@@ -2,6 +2,7 @@ package chisel3
 
 import chisel3.stage.ChiselStage
 import firrtl.AnnotationSeq
+import firrtl.seqToAnnoSeq
 
 object getVerilogString {